Oh damn, you're good! Yes, that particular USB I/F for the keyboard will most likely be attached to the bottom Master Spartan 6. If I run out of pins on the Master Spartan 6, then I don't think it would be a problem dumping hi-speed data into one of the RAMs controlled by the slave Spartan 6 using another USB hi speed contoller.

I should really finish this day checking the pin counts. I really appreciate your help!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Don't hesitate

My pleasure; and if you ever get this baby up and running don't forget to post news!


Regards,
Arne

I'll be making more videos too. Like these

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I'm a bit puzzled about those two FT232H chips in the block diagram.

Correct me if I'm wrong:
It doesn't come out clearly from the FT232H datasheet, but I think the FT232H is a USB Slave,
designed to work as a bridge from USB to RS232\FIFO\SPI etc.

Interfacing a USB keyboard or a USB memory stick to the FPGA would require a USB Host.
Please check.

It doesn't explicitly say if it's a USB host or slave device. I think it has the potential to be both? as it says multipurpose. But thanks for pointing that out. What attracted me to this IC was the royalty free drivers available for Win10 64-bit. Maybe more searching on FTDI's site might yield a better solution. I'm tempted to just go with 2 MCP2200's as they are much smaller, however their royalty free drivers are spec'd for WinXP and Win7, which I guess I could run in compatibility mode? Not sure, but when I used the Tx/Rx mode on the MCP2200 I was able to push crazy speeds sending data from the PC. I forget the terminal program I was using ... It's here somewhere.

Regarding the A21 line and extending the SyncRAMs to 4Mx18 using 2 of them, they have separate active low and active high chip enables so only one more pin needed from the FPGA. Also, since the memory has doubled I was checking into 4K transmitters. I don't think that's going to happen as my RAMs are limited to 250MHz.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Sorry: To me, it looks like the MCP2200 is a USB Slave.

Please take a look at the Maxim MAX3421E USB Host\Slave. // I don't have any practical experience with that chip.

Now, that I have realized that the Spartan6 do not have USB functionality (I thought they were capable) I understand why you are looking for an USB master chip

Perhaps another FPGA that intrinsic supports Highspeed USB 2.0 is an option for you? This third FPGA could then distribute and collect data via fast SPI within the system.


Regards,
Arne

Microchip PIC32MK family of microcontrollers seems to have chips with two USB ports,
each port able to work as USB Host or USB Slave.

Pro: PIC32 in the system also probably could be used as a "debugger" for the FPGAs.
Con: Writing the software for the PIC32 will require some work... and won't be fun.

Hmm... it's a pity, that the PIC32MK family doesn't seem to have an Ethernet controller already integrated on the chip... yet.

Edit: if somebody happens to know a microcontroller with 2 USB Host\Slave ports which isn't from Microchip, please post it here.

The STM32H753xI seems to have 2 distinct USB IFs plus Ethernet and a few things more.

(Be warned: hard stuff, datasheet = 232 pages, reference manual (w/o CPU) = 3247 pages)

After looking at USB I/F's needed for fast data transfer, including ones found at Opencores.org, I've decided to abandon USB for this purpose. It's just too complicated and I can't afford to spend time on experimenting with it.

I'm going back to the SD Card I/F. That interface will most likely be one from OpenCores.org... I'll be keeping the MCP2200 for the keyboard and it can double for rudimentary file transfer from the PC @1Mb/sec. I just read an updated version of the MCP2200 datasheet and the drivers are compatible with Windows 10.

One step closer to board design. Not had a chance to work with the 65Org16 yet.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Sorry for the slow progress but I finally got around to the availability of I/O pins on the bottom Master Spartan 6. Great news is that there should be about 22 pins available for the communications port going to the Slave Spartan 6. Wide enough to place a 4M address...

All this is for future development purposes as I'll be concentrating initially on the 65Org16 Assembler, not graphic state machines except for maybe character magnification. But if I spend the time and $$ on the board design I would like it to have as much potential as possible with those IC's so please bear with me at this development stage.

A few changes to the General Layout:
1) Master and Slave Spartan's are labelled and keyboard/PC interface is attached to the Master.
2) The MCP2200 USB to UART has replaced the FT232. Using the VQFN package, 5mmx5mm.
3) HDMI Transmitter has been relabelled. I still have yet to show programming connections from the slave Spartan 6 to this IC. Another QFN package.
4) There is now a common pixel clock among all the SyncRAMs so everything is guaranteed to be synchronized.
5) SDHC has been chosen for large/fast file transfers. It's looking like a SPI core? I hope I can do this!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Block diagram looks nice. (Do we need buffers\level_translators between FPGA and SD card ?)
BTW: It's a pity, that TDA19988, ADV7511 and TFP410 have different pinouts\packages. (Because availability of these chips may vary.)

One nice thing about Xilinx FPGAs is you can spec the I/O voltage levels per pin. For those SyncRAMs that I was able to find, I have to set those I/O pins at 2.5V. For the TDA19988 interface, those I/O pins have to be 1.8V. Most everything else will be 3.3V which is max output voltage. You can also specify slew rate as Fast or Slow and also spec output current per pin.

The ADV7511 looks nice but has 100 pins vs 64. The TI part looks like it's geared for DVI connections, 3 of them which is interesting.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

This is probably going to be the last block diag I work from in order to start the board routing. Will be 4 layer, size yet to be determined. I'll show my setup on how to solder QFN packages and individual SMD cap's and resistors when that time comes!

Last major addition was the 32Mb SPI FLASH for non-volatile storage. Will try to find one larger in size, but this one is only $4.50US. Why not add it? All I/O is just about Max'd out on both Spartan 6's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I started to panic a little today with all those different voltages. My last project, everything was using the Xilinx 3.3V LVTTL spec. I was reading the UG381 IOB spec today and for this project I'll be using the LVCMOS spec which allows 1.2V, 1.5V, 1.8V, 2.5V and 3.3V. It's sort of difficult to read but I believe any pin per IOB can be assigned any of those voltages, as long as the entire IOB is using the LVCMOS spec. Can anyone confirm this?

In preparation for my worst fears, I made most everything a 1.8V standard, the SyncRAMs are capable of this. The UG381 guide also mentioned to use LVCMOS when performing FPGA to FPGA communication so I'm confident there.

I'm going to run a project through ISE and experiment with the constraints file in order to see if it generates any errors.

Also, I may lose a few pins on the Inter FPGA Comm channel. There are some multi-function pins that are best left unused for 100% reliability. Still doing research.

EDIT: Deleted updated Layout.e

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65Org16:https://github.com/ElEctric-EyE/verilog-6502