The result is the Throw-Together-Computer © (aka TTC), and its original raison d'etre was to demonstrate my ultra-minimal 3-wire bootloader. Not surprisingly, creeping feature-ism set in, and it became more than a one-afternoon project.
I won't try to describe all the prospective experiments here. Instead it's the construction techniques I want to document.For reasons of economy I use solder-tail (rather than wire-wrap) IC sockets in several places. And for reasons of laziness I exploit opportunities for broadside bus connections, such as the 8 pins of the 40-pin DIP 65xx's databus which connect directly to the '245 transceiver that's immediately adjacent (see the annotated photo near the end). That's a real labor saver since those connections are only .1" long and don't cross over other one another... and that means they don't involve an insulated wire which needs to be stripped at both ends.
The other side of that '245 transceiver also has stuff (SIP resistor arrays) located immediately adjacent for the same reason. BTW it's not a bit uncommon for a wire (or group of wires) to attach with solder on one end and with wire-wrapping on the other. Whatever works!
). Also, notice how easy the .050" pin spacing is to deal with -- just two staggered rows of .1". These are supposed to be SMD chips, but it doesn't take much to uncurl their J leads and situate them on a .1" grid. To make the RAM assembly removable I chose to use a daughterboard that includes female headers that mate with the gold-colored male pin layout you see in the background. A cheaper but more permanent approach would be to solder directly to the main board.
The PLCC-84 -- a 128-macrocell CPLD -- could have (and maybe should have) been mounted with the same technique as the RAM's. For me it's a big priority to attach bypass cap's directly to the IC package -- attaching merely to the socket is a compromise I prefer to avoid. But instead of using a daughterboard I opted to socket the CPLD... and the socket in turn attaches to wire-wrap pins via the method described here. And: the chip is inserted upside down so I could solder some SMD caps directly onto its J leads!
That worked out alright, but I discovered that the PLCC when upside down won't snap in to the socket 100%, and I was obliged to solder it in place. To do that I firstly had to mill away part of the socket. The thing ended up with kind of a rustic look, but the bypass caps ended up where they need to be, and that's the main thing.
Unlike the large CPLD (which is entirely reserved for experimentation) this smaller device has well-defined functions. It receives asynch communication at 115.2 kbaud from a host computer, and it features a byte-wide output and a bunch of individually addressable single-bit outputs which the host can wiggle by remote control. These outputs serve to boot up the 65C02 (or '816 as the case may be) and to provide it with reset and a clock signal -- the latter being either single-step or a free-running 920 kHz (half the 1.8432 MHz communications oscillator frequency).
-- Jeff
