Project: semi-fail - suggestions please

[MichaelM]

That's great. Here's to your continued success.

[BigDumbDinosaur]

BillO wrote:

Just in case anyone is interested in what this looks like, I'm attaching a couple of photos. I'll do a little write up (and another project) at some later point. Perhaps when I get new boards made up. It's so cheap these days.

Looks good, and in Canadian Red too.

[Dr Jefyll]

Nice work, Bill -- congrats!

Those protoboards (plugged into the slots) look pretty sweet, too. Are those also your own work, and are they available for sale? More info (a proper photo?) would be nice...

[BillO]

They are my own work. I did then double sided so I could mount parts on either side if required. If you use Diptrace (or download the free version) I can send you the file for them and you can modify them as you wish. I could even create a library with the finger connector which is a 36 pin.

I got 10 of them made up at JCLPCB for $2 plus shipping.

Images attached are of the top and bottom.

[BillO]

BigDumbDinosaur wrote:

BillO wrote:

Just in case anyone is interested in what this looks like, I'm attaching a couple of photos. I'll do a little write up (and another project) at some later point. Perhaps when I get new boards made up. It's so cheap these days.

Looks good, and in Canadian Red too.

There is even a little flag on the bottom. You gave me the idea for the flag about 6 years ago or so. It goes on all my boards now.

[BillO]

GaBuZoMeu wrote:

BillO wrote:

Everything is now dancing the same dance.

Yes, correct. The timing charts of WDCs 6502 are referenced to Phi2 (in). I'm used to the NMOS charts where Phi2 (out) is referenced. But there is no information about the delay between Phi zero in to Phi 2 out, except for an old Commodore datasheet where they say its 5 ns. And 5 ns wouldn't matter anyway.

And yes, the board is looking very nice!

Here are various timings on the clock for various set-ups. Quite a difference.

This first one is PHI2in vs PHI2out on a W65C02S running at 14mHz. You can see PHI2out (yellow) lags about 5nS on the rise and about 3nS on the fall. It's easy to see why, if 6nS delay in PHI2 going to a 65C51 is enough to throw the train off the rails, WDC don;t want you using PHI2Out for the system clock in fast environments.

From here on yellow is PHI0 (clock in) - sorry about the change...

This next one is and NMOS 6502B over clocked to 5mHz. PHI2 lags PHI0 35nS on the rise and 18nS on the fall.

Here is a NMOS 6502A at 1.8mHz.

And finally, an R65C02P4 at 1.8mHz.

[GaBuZoMeu]

Thank you for the pictures!

Luckily the trailing edge delay of the NMOS parts are not that much that negation of /WE appears before data is settled - at least according to specs I found in the Synertek 1981_82 data catalog.

[BigDumbDinosaur]

BillO wrote:

BigDumbDinosaur wrote:

BillO wrote:

Just in case anyone is interested in what this looks like, I'm attaching a couple of photos. I'll do a little write up (and another project) at some later point. Perhaps when I get new boards made up. It's so cheap these days.

Looks good, and in Canadian Red too.

There is even a little flag on the bottom. You gave me the idea for the flag about 6 years ago or so. It goes on all my boards now.

Ah-ha! Cool!

[kakemoms]

Ouch! Thats a really bad clock slew. Fast components and low slew rate is a poor combination.

[BillO]

kakemoms wrote:

Ouch! Thats a really bad clock slew. Fast components and low slew rate is a poor combination.

Which one are you talking about, the top one? If you look carefully it has a slew rate of over .7V/nS. Do you really consider that slow for this application?