GaBuZoMeu wrote:
BillO wrote:
Everything is now dancing the same dance.
Yes, correct. The timing charts of WDCs 6502 are referenced to Phi2 (in). I'm used to the NMOS charts where Phi2 (out) is referenced. But there is no information about the delay between Phi zero in to Phi 2 out, except for an old Commodore datasheet where they say its 5 ns. And 5 ns wouldn't matter anyway.
And yes, the board is looking very nice!
Here are various timings on the clock for various set-ups. Quite a difference.
This first one is PHI2in vs PHI2out on a W65C02S running at 14mHz. You can see PHI2out (yellow) lags about 5nS on the rise and about 3nS on the fall. It's easy to see why, if 6nS delay in PHI2 going to a 65C51 is enough to throw the train off the rails, WDC don;t want you using PHI2Out for the system clock in fast environments.
Attachment:
PHI2IvsPHI2O.jpg [ 71.95 KiB | Viewed 3933 times ]
From here on yellow is PHI0 (clock in) - sorry about the change...
This next one is and NMOS 6502B over clocked to 5mHz. PHI2 lags PHI0 35nS on the rise and 18nS on the fall.
Attachment:
PHI0vsPHI2-nmos-oc.jpg [ 75.35 KiB | Viewed 3933 times ]
Here is a NMOS 6502A at 1.8mHz.
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PHI0vsPHI2-nmos.jpg [ 69.83 KiB | Viewed 3933 times ]
And finally, an R65C02P4 at 1.8mHz.
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PHI0vsPHI2-cmos.jpg [ 67.98 KiB | Viewed 3933 times ]
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