Dear 65x02 fans
I found this threat while searching for r65c02_tc related topics over the internet.
I'm Jens Gutschmidt, the developer of the r6502_tc and r65c02_tc IP core. Designed for FPGA solutions which have real time requirements for internal and external cycle relationship.
I'm also very glad and thankful that my work was discussed here in that nice community! THANKS to all!
I'm sorry about my poor English and I hope, my posts produce no more questions they are able to answer
I found a very interesting comparison table between some hdl soft core implementations of 6502 in 2010 here. Also the discussion around this is very interesting and show important things for the future.
Because my r65c02_tc IP core will be change its state "BETA" to "PRODUCTION" soon, I have some ideas/questions to you all.
1. It is time for a new and actualized version of the comparison, I found.
2. In the past the comparison based on area related issues and only Xilinx. Altera should be added. Also fmax.
3. There are question about fmax related issues in the community, right? The way of synthesis was not discussed enough in the past I found.
4. The capabilities of each soft core is not clear enough. (e.g. "RDY" signal or not)
I played around tool capabilities (Xilinx vs. Altera, settings and project format VHDL/EDIF) to verify area and speed results. There are drastic differences between the results.
I would imagine, that the end user is overwhelmed to make the right decision for its project in most cases.
Low-end development tools like Xilinx and Altera web editions are not optimized to process and synthesize pure VHDL/Verilog sources for best area/speed results. Only high valued tools are able to do this job because the know-how to do this, is very very expensive you know...
There are questions like "Is there a 6502 core runs over 50MHz around?" It is not only a question about the quality of the core. It is also a question about the quality and capability of the tool itself.
If your project is depend on speed or area requirements, using of the right tool is a requirement too.
You can speed up your design up to 80% (more is possible) by using the right tool.
Anyway - back to the thread.
As developer of IP cores it is possible to give pre-synthesized cores (EDIF format) to the public. These cores are technology and vendor depend but optimized (area/speed).
If the most people here working with e.g. Xilinx' SpartanX, it is a requirement to the developer to offer optimized cores via pre-synthesis if possible. Only patching the VHDL/Verilog sources by the end-user is not the solution!
Please remember, that a core at no-cost doesn't have the quality of a payed one. The opencores.org projects are based on no-profit...
Please tell me, what you need to finish and fulfill your projects.
So, what do you think about refreshing the comparison table with actual and more information?
I can do the synthesizing comparison between Altera, Xilinx and third party high valued tools (area & fmax).
Also I can give specific or general information about area/fmax related issues - not only about my own core sources...
Thanks
Cheers
Jens