Dear 65x02 fans

I found this threat while searching for r65c02_tc related topics over the internet.
I'm Jens Gutschmidt, the developer of the r6502_tc and r65c02_tc IP core. Designed for FPGA solutions which have real time requirements for internal and external cycle relationship.
I'm also very glad and thankful that my work was discussed here in that nice community! THANKS to all!
I'm sorry about my poor English and I hope, my posts produce no more questions they are able to answer

I found a very interesting comparison table between some hdl soft core implementations of 6502 in 2010 here. Also the discussion around this is very interesting and show important things for the future.
Because my r65c02_tc IP core will be change its state "BETA" to "PRODUCTION" soon, I have some ideas/questions to you all.

1. It is time for a new and actualized version of the comparison, I found.
2. In the past the comparison based on area related issues and only Xilinx. Altera should be added. Also fmax.
3. There are question about fmax related issues in the community, right? The way of synthesis was not discussed enough in the past I found.
4. The capabilities of each soft core is not clear enough. (e.g. "RDY" signal or not)

I played around tool capabilities (Xilinx vs. Altera, settings and project format VHDL/EDIF) to verify area and speed results. There are drastic differences between the results.
I would imagine, that the end user is overwhelmed to make the right decision for its project in most cases.

Low-end development tools like Xilinx and Altera web editions are not optimized to process and synthesize pure VHDL/Verilog sources for best area/speed results. Only high valued tools are able to do this job because the know-how to do this, is very very expensive you know...
There are questions like "Is there a 6502 core runs over 50MHz around?" It is not only a question about the quality of the core. It is also a question about the quality and capability of the tool itself.
If your project is depend on speed or area requirements, using of the right tool is a requirement too.

You can speed up your design up to 80% (more is possible) by using the right tool.

Anyway - back to the thread.
As developer of IP cores it is possible to give pre-synthesized cores (EDIF format) to the public. These cores are technology and vendor depend but optimized (area/speed).
If the most people here working with e.g. Xilinx' SpartanX, it is a requirement to the developer to offer optimized cores via pre-synthesis if possible. Only patching the VHDL/Verilog sources by the end-user is not the solution!
Please remember, that a core at no-cost doesn't have the quality of a payed one. The opencores.org projects are based on no-profit...

Please tell me, what you need to finish and fulfill your projects.

So, what do you think about refreshing the comparison table with actual and more information?
I can do the synthesizing comparison between Altera, Xilinx and third party high valued tools (area & fmax).
Also I can give specific or general information about area/fmax related issues - not only about my own core sources...

Thanks
Cheers
Jens

Hi Jens, great to see you here, and welcome.

You are quite right, the comparisons are based on minimal human effort (and even so they take some time to sort out) so very fine distinctions between cores will not show up, but perhaps the very coarse differences will.

I think I volunteered at one time to rerun the evaluations on the latest Xilinx toolchain and targetting Spartan 6, but I have not done anything towards that. We do still see projects using Spartan3 and indeed I have a few Spartan 3 devices to play with and only one Spartan 6. So, evaluating with the latest devices will not necessarily satisfy everyone.

It would be great to get some comparisons with a different vendor, and also to see comparisons where some effort and expertise has been applied to minimise cycle time or area.

If you take the trouble, please do post your results!

Cheers
Ed

Jens:

Great to have you join us. I looked at several implementations, and some of them I even implemented in order to develop a cross-reference table.

I would be interested in working with you to develop another cross-reference to be posted on this forum. I am quite tied up at work during the week, but I could set aside some time on weekends.

_________________
Michael A.

I am happy to announce that I have Arlet's core running on an XC3S50-(grade 5) at 50MHz, with a 10ns 128K SRAM. The core along with all the decoding logic and a UART fit into just about 1/2 of the available resources, with 3 BRAMS unused.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Hello Ed and Michael

Thanks for valuable and nice feedback.

It might be a heavy job to work on a new cross-reference. There are new 6502 soft core variants around with new capabilities and performance borders.
I found many Spartan3 projects on the web are still active. But found less based on Altera.
Before posting something more I'll surfing around the "Cape of 65c02" twice or more.

Anyway - I have also some open tasks around my cpu65c02_tc finishing this week. I'll be glad for any help to begin a new big one task like cross referencing 65x02 soft cores ...

-> Michael
The last cross-referencing found here in 2010 is a very good base to go further on, I found.
I propose to collect some facts before we'll start. I hope you agree with that. May be some other 6502 fans will support us.
Let us talk more about this at the next weekend.

Meanwhile I'll take a look to the brain storming in my head...

Cheers
Jens

Nice to see you here Jens! I remember seeing your work on OpenCores.org years ago, although I had no interest even of learning HDL
It would be great if a team would go into more depth about 6502 cores, even if it weren't with the Xilinx family of FPGA's. I've read some certain things that Xilinx is headed towards clinching the larger FPGA market for the future. So IMO we all need to keep our collective eyes open for the manufacturer that has their eyes on the smaller FPGA market niche.

Interesting read here posted by Gabor of the Xilinx forums.

EDIT: Added info.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

On the other hand, XC3S50's can be picked up for next to nothing, and offer an amazing amount of power for the price.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Thanks for reply and additional information!

I planned to investigate both main target technologies Xilinx and Altera. The most effort might be to held the collection/comparison up to date.
I also think, that older types of FPGA chips are interesting for most users today. Day by day new users start with hdl and/or cheap FPGA boards.

The first comparison will include
- Altera Stratix...Stratix V, Cyclone...Cyclone V
- Xilinx Spartan 3....Spartan 6, Virtex family

Suggestions and ideas are very welcome.

Cheers
Jens

I've had a Cyclone II board (with tons of RAM on-board) in a drawer for a year.. I've still not wrapped my head around how to really get started with FPGA. As I briefly mentioned in totally different thread these types of GUIs tools don't work for me (_nothing_ is where I would expect it to be) so I haven't been able to "play" with it. It would be great to find some use for that board though - it's got lots of features.

-Tor

Hi Tor

And why do you bought this fine board? What of ideas at the beginning do you had?
It is too bad to have a CycloneII in a drawer only, I think too...

What is name of the threat you referenced for?

Cheers
Jens

I'm not a big fan of complicated IDEs either. However, the eval board I got came with a simple step-by-step guide to get a demo project running. At first I followed the exact steps. Then I used my own favorite editor in another window to edit the files, made a Makefile to run simulations with external simulator, and only used 2 commands of the IDE to build the project once in a while.

I also use a makefile to invoke Xilinx tools. I can't stand the GUI personally.

_________________
In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I've been playing with Arlet Ottens core (using the stock latest code from github) on a zynq 7020. It happily meets timings (ie: post place/route) with an 11ns clock (50% duty cycle for ~91 MHz) and has the following utilisation:



10ns is just beyond the capabilities of the -1 part that's on the Arty-Z7 board. The failing 5 paths at 100MHz are all setup in the C->ALU/* routes.

Just FYI if anyone's interested

I came across MCL65 not too long ago.. Seems to be cycle accurate and fully microcoded using a 2Kx32bit ROM. Link here:

http://www.microcorelabs.com/mcl65.html

While it *claims* to come in at around 250 LUTs on a Spartan 7, compiling it for a Cyclone II yields an unfortunate 670LE beast. Still good, but not great.

Yvo

Interesting. I have not yet tried to fit the MCL65 to a Cyclone device. Still, your number is about 14% in the smallest Cyclone II family which doesnt seem too bad.

The MCL65 supports all of the 6502's bus signals including SO, SYNC, CLK1, CLK2, so maybe the size would be smaller if they were removed. I dont believe the Arlet core supports these signals, so perhaps it could not be used in an Atari-2600, VIC-20, or an Apple-II as the MCL65 can.

https://www.youtube.com/watch?v=_5xzskexh-o
https://www.youtube.com/watch?v=wYX0pCn0OMg