I wouldn't say it's an achiles heel, but it partly holds the key to why the 65xx's performance is so high for its clock rate compared to its contemporaries.
The clock is definitely the achilles' heel for the 65xx family. If the slew rate is too slow, the internal operation of the CPU becomes unstable. If the address decoders aren't gated by the clock, then you get memory corruption. Etc.
These reasons are why FPGA and other high-density logic chips use fully synchronous designs. For example, the Wishbone bus can be thought of as a 2nd-generation 65xx bus -- single-cycle reads and writes, 32-bits with individual lane strobes, etc., pickles and onions, and a side of ketchup, to go please. Yet, it does everything
NOT with high-level or low-level logic. (or worse, both). Instead, everything is clocked on the
rising edge of the clock. And I do mean
everything. There literally is absolutely no exception to that rule.
I suppose one can say that the 6502 bus is similar, since everything is clocked on what appears to be the falling edge of phase 2. But the 65816 is a whole different beast, managing its bus with both edges, and in the case of the bank address, *levels* as well.
It is for this reason that the 65816 needs to have such a pristine clock source. Without it, it starts to malfunction in seemingly random ways.
You'll be amazed at the RF hash that comes out. Remember: the 65816 has *fast* transitions on its signals, so it still puts out VHF or better frequencies.