Random questions.

[LBSC]

1st: did the original 6502 use edge triggered D flip flops or other type of memory?
2nd: is it okay if I build the control logic with ROM instead of hardwiring it?
3rd: which type of adder did the 6502, RCA or CLA?

[BigEd]

1. The 6502 uses transparent latches - some people call these half-latches. You need two transparent latches, and a non-overlapped clock, to make a flip-flop. Many parts of the 6502 can be viewed as having pairs of half-latches like this, but many other parts of it place logic between the two latches. Sometimes you even get two half-latches in series clocked off the same edge. However, see for example Arlet's 6502 in Verilog, it is possible to make something very like a 6502 but only using edge-triggered design.

2. Yes, 6502 workalikes have been made using memories to implement the logic. You can always use asynchronous memory to act as a look up table and perform logic. Indeed, that's how FPGAs work, inside, you have a huge number of small look up tables.

3. The 6502 uses ripple carry in the ALU. For the PC incrementer, there is a look ahead, so the low byte has a ripple, there's an FF detector, and the high byte has a ripple.

See also Andrew Holme's page:
viewtopic.php?f=10&t=4295

See also [org]'s breakNES project, with reconstructed schematics of the 6502 implementation:
http://breaknes.com

[LBSC]

Whoa Ed, thank you so much! Now things are more clear and specially the 6502 schematics with logic gates
Do you have any schematics of the program counter?

[BigEd]

You should have a look over Balazs' giant schematic - I think it was the first effort to reverse engineer the 6502. There are a few omissions and maybe some errors but it's a very good reference and also a map:
http://www.visual6502.org/wiki/index.ph ... _documents
(The orientation is different from the visual6502, but it's only like driving South. You don't really have to turn the map upside down.)

[BigEd]

(Oh, and also look over org's thread:
viewtopic.php?p=26678#p26678
It turns out there's more in the thread than on the website I linked to.
)

[BigEd]

(I notice Balazs calls the Program Counter the Instruction Pointer. It's top left, more or less.)

[LBSC]

BigEd wrote:

(I notice Balazs calls the Program Counter the Instruction Pointer. It's top left, more or less.)

Which one? There are a lot of photos in that site.

[LBSC]

BigEd wrote:

(Oh, and also look over org's thread:
viewtopic.php?p=26678#p26678
It turns out there's more in the thread than on the website I linked to.
)

Is that a CLA?

[BigEd]

LBSC wrote:

BigEd wrote:

(I notice Balazs calls the Program Counter the Instruction Pointer. It's top left, more or less.)

Which one? There are a lot of photos in that site.

I was referring to Balazs' giant schematic:
single page schematic 730kByte pdf

I did previously link to
Atari's 6507 Schematics
which is worth looking over, I'm sure, but I've never studied it. There's a sheet labelled PC counter which makes little sense to me (at a quick glance) - my previous link to this page was about the ALU, to answer your question about the ripple carry.

LBSC wrote:

BigEd wrote:

(Oh, and also look over org's thread:
viewtopic.php?p=26678#p26678
It turns out there's more in the thread than on the website I linked to.
)

Is that a CLA?

Sorry, I don't understand... the post I linked has the text: "Todays speccy: Program Counter logic circuit" with a logic diagram of the PC circuit.

[ttlworks]

LBSC wrote:

Is that a CLA?

CLA = Carry lookahead adder.
Looks like the PC incrementer and the ALU use ripple carry...
but the polarity of the carry is inversed for every second Bit.

BTW: something about the NMOS 6502 ALU is here.

Edit:
BigEd certainly knows the NMOS 6502 architecture better than ttlworks.

[BigEd]

BigEd wrote:

LBSC wrote:

BigEd wrote:

(Oh, and also look over org's thread:
viewtopic.php?p=26678#p26678
It turns out there's more in the thread than on the website I linked to.
)

Is that a CLA?

Sorry, I don't understand... the post I linked has the text: "Todays speccy: Program Counter logic circuit" with a logic diagram of the PC circuit.

Ah, thanks ttlworks, now I notice CLA is carry-lookahead adder. Well, the PC incrementer is only an incrementer, not an adder. But yes, as I mentioned, there is an 8-input gate to detect when the low byte is FF, and so there is some lookahead, and you can see that gate in org's schematic. We also see a 4-input gate which detects the bottom nibble of the top byte as F, which is another small amount of lookahead. Broadly, instead of a 16 bit increment, we have an 8 bit increment, and in parallel to that we have a 4 bit increment after a couple of gates of lookahead calculation. You can see some indication of this structure in Hanson's block diagram.

(There are many possible architectures for carry lookahead addition, and presumably about as many for carry lookahead incrementation. There's a tradeoff of how many transistors to spend on speeding up the carry path: there's a point where it's no longer worthwhile, either because it costs too much or because it is no longer the critical path of the system as a whole.)

[LBSC]

BigEd wrote:

BigEd wrote:

LBSC wrote:

BigEd wrote:

(Oh, and also look over org's thread:
viewtopic.php?p=26678#p26678
It turns out there's more in the thread than on the website I linked to.
)

Is that a CLA?

Sorry, I don't understand... the post I linked has the text: "Todays speccy: Program Counter logic circuit" with a logic diagram of the PC circuit.

Ah, thanks ttlworks, now I notice CLA is carry-lookahead adder. Well, the PC incrementer is only an incrementer, not an adder. But yes, as I mentioned, there is an 8-input gate to detect when the low byte is FF, and so there is some lookahead, and you can see that gate in org's schematic. We also see a 4-input gate which detects the bottom nibble of the top byte as F, which is another small amount of lookahead. Broadly, instead of a 16 bit increment, we have an 8 bit increment, and in parallel to that we have a 4 bit increment after a couple of gates of lookahead calculation. You can see some indication of this structure in Hanson's block diagram.

(There are many possible architectures for carry lookahead addition, and presumably about as many for carry lookahead incrementation. There's a tradeoff of how many transistors to spend on speeding up the carry path: there's a point where it's no longer worthwhile, either because it costs too much or because it is no longer the critical path of the system as a whole.)

I know what a CLA is, but I can't see a single piece of circuitry in that CPU that looks like a CLA. Where'd Donald F. Hanson get the lookahead in the NMOS 6502?

[BigEd]

Look at the PC. It's only an incrementer - a much simpler thing than an adder, and much easier to add lookahead as you only need to detect all-ones in the area of interest.

[LBSC]

BigEd wrote:

Look at the PC. It's only an incrementer - a much simpler thing than an adder, and much easier to add lookahead as you only need to detect all-ones in the area of interest.

Oh, do you know any CLA design that is not as messy as mine?

[BigEd]

I don't know what yours is like! Wikipedia has this note:

Quote:

The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits of the adder. The Kogge-Stone adder and Brent-Kung adder are examples of this type of adder.

- https://en.wikipedia.org/wiki/Carry-lookahead_adder

I'm sure there's a lot of reading one could do on this.