So I'm on vacation this week and for fun, I decided to add a 65C22 to my Apple IIe.

I can give a schematic if you like but the setup is pretty simple.



As you can see, I use an inverted A7 which goes though a simple hex inverter.

For the clock, I use PHI0 inverted 3 times to add a slight delay. I got that circuit idea from the Mockingboard clone by Bill Garber.

I have my prototype in slot 4. So this means with /IOSEL and an inverted A7, I get the following addresses:



Next, I wrote a simple BASIC program that just sets port A to all output and then cycle 0-255. Works great. I can see my LED's light up.

But I have one issue. In order for me to set a value to ORA like 128, I must set DDRA every time! So if I change ORA to 129, all my LED's go blank. I set DDRA again and 129 lights up.

What am I doing wrong? Surely this can't be right.

Here is the actual BASIC code I'm using:




That works. But if I remove line 45, all of the LED's are blank.

Thanks

_________________
Cat; the other white meat.

Three times? Sounds fishy to me, although I'm not especially an expert on the iie and Mockingboard. But in 65xx jargon PHI0 (phi zero) is more or less the same as Phi2. Seems to me you might pass PHI0/PHI2 directly (ie, with zero inversions) to the 6522 PHI2 input, or invert it twice or four times (all even numbers). But to me three inversions seems very weird. As an experiment, can you easily reduce it to two inversions? I suggest you try that and report back.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Actually, I tried that originally. I first had PHI0 directly and I never could make the LED's light at all. Next I tried PHI2 and same thing. Never lit up. So, I did the three inversions. I can try reducing that down and see what it does.

**EDIT**

Nope. Does the same thing. Not sure why. If I invert PHI0 2x then I get nothing. 3x and I get what I expect but I still have to set the DDR each time.

_________________
Cat; the other white meat.

Not what you'd call success, then. It may seem one step closer but that could be misleading.

Can you link us to some doc on the IIe? I'd like to confirm whether the PHI0 signal you mention corresponds to the PHI0 pin on the 6502. If it does then three inversions is wrong.

Edit: What inverter IC are you using? Also, is it a WDC 65c22 you're using? There might be an issue with logic levels. WDC's W65C22S needs CMOS levels, but I suspect the IIe may have only TTL levels for some/all signals on the expansion bus.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I concur with Jeff. Three inversions would put Ø2 at the VIA 180 degrees out of phase with the microprocessor's notion of the clock.

Like Jeff, I'm no expert on the Apple ][e hardware, but a 6502 is a 6502, no matter the machine. I think you need to re-examine what you are using for a clock source. Likely, the real Ø2 is derived from the output of the 6502 at pin 39. The 65C22 must be driven by that clock in order for it to properly function. Address lines, chip selects and R/W must all be valid and stable prior to the rise of Ø2.

Also, as Jeff noted, this may be the classic TTL driving CMOS logic level problem if using the 65C22. Some Apple ][e models were shipped with 65C02s but that doesn't mean the peripheral devices were CMOS-compatible. Ostensibly, the 65C22N is a drop-in replacement for the older 6522, but that doesn't necessarily mean it will be 100 percent compatible with the Apple ][e's glue logic, much of which was implemented on a custom ASIC that may have included features to efface logic level differences.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

This is a known issue with the Apple II bus. The problem is that the per-slot chip select lines of the bus, DEVSEL, IOSEL, and IOSTROBE, have the system clock as part of the logic generating the signal and, for a 6522 or even most 65xx series chips, shouldn't. Delaying the clock input to the 6522 is the only solution but using inverters to do it varies quite a bit on how well it works depending on the speed of the inverters and the 6522. Apple published a tech note with a schematic using a 74LS74 and other bus clock signals to get a defined delay that is supposed to work in all cases. You can find a copy of it at https://archive.org/details/Apple_II_HW_6522_VIA

That sounds like what I did for a C64 expansion board I made many years ago with a pair of 22's, and I ran into the same thing. What I did was this:



(from my project pages on this site, long before I had my own website). Here's the board:

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The Apple II slots are missing Phi2, but Apple had published a TIL (no: 494) in the past regarding the 6522 ICs and provided a (simple) schematic to re-create the Phi2 from Phi0 (which is available on the slots).

The TIL can be found here.

This is what I use(d) for my own projects which need Phi2

Thanks, Uncle Warthog and xjmaas for directing us to the Apple document.

Last night I was looking at the schematic that's provided, and decided to fill in some of the missing detail. Instead of just pin numbers I added the signal names on the flipflop and in a few other places. FWIW I'll share that now.According to the Apple doc, "The 74LS74 circuit delays the positive edge of the clock by one cycle of the 7 MHz clock," but to me it looks as if the delay will be "at least one cycle" or perhaps simply two cycles. But it probably doesn't matter.

Garth's circuit is a reasonable alternative to this one, and his analog delay is more easily tweakable. OTOH there's something to be said for the digital approach, which presumably won't require tweaking.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Ugh. This is frustrating. I've tried every one of those other examples. Doesn't work. It's got to be something else.

I have a breadboard next to my Apple IIe and the wires from my proto card to the breadboard are probably 9" long and I'm wondering if that's some of the issue. Especially with the signal select wires.

I might try soldering up something with shorter wires and see if that makes a difference. I wouldn't have thought a simple 65C22 to a Apple IIe would be so difficult. :-/

_________________
Cat; the other white meat.

UPDATE

OK, this is really odd. I've been trying to reduce the number of times I delay pin 38 (T1 or PHI1) and it's either not worked or was unstable.

So I went the other way and delayed it even more! I'm inverting it FIVE times now and it's working in BASIC.

However, I've been able to break it a few times by poking values in very fast and then going to the command line and poking it manually. So I don't call it a success.

But, BASIC programs that run slow and have some delay between each iteration of ORA seem to work. I've even got some animation running.

I still wished to solve this because this cannot be right.

Some things I did differently:

On the inversion of A7, I put a 1K resistor to VCC.
I put a 4K7 pullup on the REST of the VIA. The mockingboard spec didn't include that so I didn't think I needed it.

I'm going to keep digging...thanks for any suggestions.

_________________
Cat; the other white meat.

Sometimes it's easy to overlook the basics. How's the power? Measured on the project itself, are you able to verify 5 volts? And have you one or more bypass capacitors in place?

A photo might be helpful; likewise a link to the Mockinboard documentation you've been viewing.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Maybe I'm stating the obvious, but ideally what we want is to delay the rising edge of the signal at the VIA's PHI2 input and NOT delay the falling edge. IOW we'll distort the duty cycle somewhat, making it less than 50:50. The Apple circuit accomplishes this using a clocked flipflop for delay, and Garth's circuit uses a variable analog delay.

Here are some variations of another analog delay, but using propagation delay instead of an RC. Actually the version with resistors uses RC, too, with C being the input capacitance of the gate. If each resistor is 1K then each will add about 10ns, ballpark. But I doubt you'll need any resistors at all.

BTW is it a WDC 65c22 you're using?

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Possibly investing in a logic analyzer (even just a Saleae 4-channel) might be worthwhile.

Thanks again everyone for the suggestions.

@Dr Jefyll

I tried that circuit but it did not work. However, I don't have any 75HCT08's so I used a 74HCT21 and just tied two inputs to HIGH.

** EDIT **
Actually, I was able to break it in Apple BASIC. It just isn't consistent. So, if the DDRA is set and STAYS SET, then all of the ORA changes work perfectly. But it's like it forgets what direction DDRA is set and I have to do it 4-5 times before it "sticks".


To answer some questions:

1) I've checked all of the voltages...everything looks good.

2) I am using a WDC 6522. It's the 65C22 S6TPG-14

3) I have 0.1uF caps on all power pins of all IC's (only two at the moment) and plenty of large caps all over the board. I've checked the power on different sections of the board and it looks OK.

4) Attached is a schematic of how I have the VIA attached to the Apple IIe. I'm 99% sure I have everything connected correctly and voltages check out.


CRUDE video of it running....

https://youtu.be/cUxTEVbOsew

_________________
Cat; the other white meat.