Thanks for the several suggestions folks. I finally had a chance to get back to the panel, and did as dr Jefyll suggested, bracing the thing with a piece of lumber along the edge of the workbench. Applying firm pressure to the overhanging portion of the panel produced a clean break along its length. From there, I could easily snap the resulting half-panels by hand. Some fine sandpaper is all that was needed to smooth out the rough edges. Nice!
Hopefully the planes were not brought out all the way to the edge, but stop .010" or so from the cut.
The copper planes are 15mil away from all board boundaries, even those internal to the panel. I can easily see these gaps when holding the PCBs up to a light, and checking for shorts between VCC and GND confirmed there does not seem to be a problem there.
50 ns, wow, that's pretty good.
Fingers crossed on that! Below is a table showing various paths through the CPU and approximate propagation times for different logic families. The column labeled "AC+ Typ" is the relevant one for this build (i.e., mostly 74AC logic with a few 74LVC and 74CBT parts thrown in). The ALU and Microcode Fetch share top-honours as the critical path.
To get down to those (hypothetical) 50ns, it was neccessary to pull quite a few tricks.
Including pipelined microcode and some hardware logic checking for 1 Byte instructions...
As well as some fancy footwork in the ALU by ttlworks and dr Jefyll.
IIRC the microcode defaults to reading a Byte from [PC+] in memory for the cycle after an instruction fetch... for all instructions.
If the logic detects a 1 Byte instruction, it blocks writing PC+1 to PC and discards that additional Byte.
Yes, that's right.
Here is a description of the pipeline logic.
The "basic" CPU has two PCBs.
A third PCB is required to have K24 instruction set, 24 Bit address bus,
and to be able to switch between the different instruction sets by software.
I couldn't resist stacking the new PCBs with the old SBC just to have a look. It may serve as much needed inspiration for the task ahead.
I can already see it running ...
Cheers for now,
Drass
). That little mishap set me back a bit, but in fact I'm much faster now than when soldering the SBC. I've taken quite naturally to using a "drag" technique on the SOIC packages, which now feels very comfortable. Amazing what the right tools and a little practice will do.
