Connecting a AY-3-8910 to the 6502 bus.

[Martin_H]

I am connecting a AY-3-8910 and I want to double check everything, so I figured I could explain this to the forum to invoke the rubber duck debugging technique, and someone might spot an omission.

These are the bus signals on the expansion header that I am using. First the easy ones that I can use directly:

CLK2 - 6502 clock connected to P22
/Res - reset line connected to P23
D7-0 - data lines connected to P30-37

The next set are the inputs to the decode logic:
A0 - used to select latching versus latch or write.
/7F0x - from address decode logic, used to chip select.

Looking at the data sheet B2 is left unconnected and is internally pulled up. That leaves us with the following truth table:

BDIR = 0 and BC1 = 0 means inactive
BDIR = 0 and BC1 = 1 means read from register
BDIR = 1 and BC1 = 0 means write to register
BDIR = 1 and BC1 = 1 means latch register address

If /7F0x is high I want to force both BDIR and BC1 to the inactive state, and I want to use A0 to switch between write versus latching. I think this address decode logic should achieve that:

BDIR = NOT /7F0x
BC1 = /7F0x NOR A0

So while /7F0x is high both inputs are forced low, but when it goes low I can either write or latch by using an even or odd address. While I can't read from a register, I don't need to do that. I found this schematic which matches my basic ideas, so I am pretty sure I am on the right track:

http://www.armory.com/~rstevew/Public/S ... rcuit.html

Note that in my breadboard circuit I cheated a bit and used an Arduino as part of the logic, so I would like to replace that with discreet logic IC's. I also know I could use the mocking board schematic which uses a VIA, but that seems like overkill.

[Martin_H]

After looking through my parts box I realized that I had a quad NAND gate IC, not a quad NOR gate! But it is possible to swap NANDs for NORs with some logic juggling. So I replaced all NOR gates with their NAND equivalent, and then removed redundancy. They result is the same logic using three NAND gates:

BDIR = /7F0x NAND /7F0x
/BC1 = BDIR NAND A0
BC1 = /BC1 NAND /BC1

So my digital logic course comes in handy 33 years later.

[GaBuZoMeu]

It's a bit early but
BC1 = /7F0x NOR A0
is different from
/BC1 = BDIR NAND A0

me thinks it should be
/BC1 = BDIR NAND /A0

or is it too early in the morning?

[Martin_H]

In my original logic I had the sense of A0 switched to save a NOR inverter gate. But when I found the linked page they used three NOR gates. But when I switched to NAND logic it save a gate to swap the logic around to match the initial logic. But here's my work just to see if I got this right:

BDIR = /7F0x NOR /7F0x
/A0 = A0 NOR A0
BC1 = /A0 NOR /7F0x

Step one was to replace the NOR inverters with NAND equivalents.

BDIR = /7F0x NAND /7F0x
/A0 = A0 NAND A0
BC1 = /A0 NOR /7F0x

Step two was to replace the NOR with the four NAND gate equivalent using A NOR B = NOT (NOT A NAND NOT B)

BDIR = /7F0x NAND /7F0x
/A0 = A0 NAND A0
BC1 = NOT (NOT /A0 NAND NOT /7F0x)

That's six gates, but there's some factoring we can do. For example NOT /7F0x is BDIR, so we can substitute that and eliminate one gate. Also, NOT /A0 is A0, so we can use that input directly. That simplifies to four gates:

BDIR = /7F0x NAND /7F0x
/A0 = A0 NAND A0
BC1 = NOT (A0 NAND BDIR)

But /A0 is unused and the NOT can be replaced with a NAND inverter. So that yields:

BDIR = /7F0x NAND /7F0x
/BC1 = A0 NAND BDIR
BC1 = /BC1 NAND /BC1

[GaBuZoMeu]

This transformation is correct.

There is only a difference between your first post
BC1 = /7F0x NOR A0

and the latest version (post 3)
BC1 = /A0 NOR /7F0x

As I have no DS for the AY-3-8910 I cannot say which one is correct. But if the last version (post 3) is correct then
/BC1 = A0 NAND BDIR

is correct as well.

[PaulF]

Whilst your logic is correct, unfortunately, it will not work as described I'm afraid. You have not included the 6502 Phase2 clock in your logic.

You need to modify your logic so that BC1 and BDIR only go high IF the 6502 Phase2 clock is high. When the Phase2 clock is low, BDIR and BC1 should be low as well.

Also, what speed is your 6502 running at? If your 6502 clock is faster than 2MHz, you can't connect an AY-3-8910 directly to the 6502 bus because the AY-3-8912 isn't fast enough. If you have a really old AY-3-8910, it will only directly interface to a 1MHz 6502, although none of the AY-3-8910's I've ever encountered have been this slow.

When you come to programming the AY-3-8910, be aware that the data sheet for this device originally had all the numbers in octal, not hex. So register addresses on the data sheet go from 0..7 and 10..17. In hex, the register addresses should go from 00..0F. Check your data sheet carefully to see which verson you have.

[Martin_H]

PaulF, thanks for reviewing, and the suggestion. My 6502 is running at 1 MHz, so I should be OK.

If I understand your suggestion it sounds like I need to include two AND gates as follows:

BDIR = /7F0x NAND /7F0x AND CLK2
/BC1 = A0 NAND BDIR
BC1 = /BC1 NAND /BC1 AND CLK2

I assume the reason is that unless CLK2 is high I can't count the data bus contain valid data?

[GaBuZoMeu]

Data appears during CLK2 is high and should considered to be valid at the falling edge of CLK2.

[cbmeeks]

The VIA might seem overkill but the cool thing about it is that you then get at least 5-6 bits free to do a million and one other things.

[PaulF]

Martin_H wrote:

PaulF, thanks for reviewing, and the suggestion. My 6502 is running at 1 MHz, so I should be OK.

If I understand your suggestion it sounds like I need to include two AND gates as follows:

BDIR = /7F0x NAND /7F0x AND CLK2
/BC1 = A0 NAND BDIR
BC1 = /BC1 NAND /BC1 AND CLK2

I assume the reason is that unless CLK2 is high I can't count the data bus contain valid data?

Yes, both your logic and the reason for it are correct.

If you are only running at 1MHz, you should have no problem

[Martin_H]

Sleeping on this I think I only need to do the following:

7F0x = /7F0x NAND /7F0x
/BDIR = 7F0x NAND CLK2
BDIR = NOT /BDIR
/BC1 = A0 NAND BDIR
BC1 = /BC1 NAND /BC1

The reason I don't need CLK2 for BC1 is that if CLK2 is low, then /BDIR will be high. This is in turn inverted which yields a low BDIR. Since BC1 is essentially ANDed with BDIR I know that a low BDIR will result in a low BC1.

This means I only need to use the one unused NAND gate and a single transistor inverter.

Update: added a schematic​.

[PaulF]

Martin_H wrote:

Sleeping on this I think I only need to do the following:

7F0x = /7F0x NAND /7F0x
/BDIR = 7F0x NAND CLK2
BDIR = NOT /BDIR
/BC1 = A0 NAND BDIR
BC1 = /BC1 NAND /BC1

The reason I don't need CLK2 for BC1 is that if CLK2 is low, then /BDIR will be high. This is in turn inverted which yields a low BDIR. Since BC1 is essentially ANDed with BDIR I know that a low BDIR will result in a low BC1.

This means I only need to use the one unused NAND gate and a single transistor inverter.

Yes, this will work correctly. Good luck!

[Martin_H]

PaulF wrote:

Yes, this will work correctly. Good luck!

Thanks. If I get something working I will post a video.

[Martin_H]

I am using the output of a 74ls138 to select this IC. I know the 74ls138 is working because it selects my VIA and ACIA. I'm trying to use an LED on the board to monitor this I/O select, but I don't drive it directly. I drive the LED using a transistor with a 10K base resistor and a 1K current limiter. Since the /7F0x is normally high (verified using my DMM) I would expect the transistor to switch on, and the LED to be on. So far so good.

When I write to 7F00 I would expect /7F0x to go low, turn off the transistor, and turn off the LED. Now given that many other addresses are being written to this would be brief, but if I did it in a tight loop I was hoping to see the LED dim a bit. But no luck it always looks bright.

Any tips for monitor this output?

[GaBuZoMeu]

If you tie the select output to the CPUs RDY input it should stop.