Lessons Learned...total failures

[BigDumbDinosaur]

floobydust wrote:

If I were to do this again, I would do it a bit differently;
1- A different pinout for the I/O connector making it more flexible for using other I/O devices
- 32-bytes wide (rather than 16-bytes)
- Positive going Reset line
- Cleaner signal distribution on the 30-pin connector

A low going reset should still be present for maximum flexibility.

Also, more related to construction than design, ideally each signal in the cable should be separated from the next signal by a ground. In other words, ground -- signal -- ground -- signal --, etc. This is a technique seen in some disk drive cables (the single-ended SCSI bus, for example) the helps to reduce crosstalk.

Quote:

2- Use a CPLD for glue logic so I can alter the ROM/RAM-I/O addressing

Not only does that give you some flexibility in overall design, it opens the door to adding features that aren't very practical with discrete logic, such as different memory map combinations.

One of the limitations of my POC V2 design is I opted to use Atmel's (now Microchip's) small ATF1504AS CPLD, which is PLCC44. That decision was based upon the desire to keep my PCB size within the Express PCB Proto-Pro size and hole count limits. As a single PLCC socket can add quite a few holes, I went with the smallest available, which was the PLCC44.

While the 1504 has ample logic resources (64 macrocells), it only has 32 uncommitted I/O pins, which proved to be significant as the design evolved. Every pin is in use and I had to allow the fitter to automatically choose all pin assignments except for the clock and reset inputs. As you could imagine, this added complication to laying out the PCB, since I couldn't use a "best fit" methodology to decide how to route the board. As I am using a different source at this time for POC boards, I'm less constrained with the size and hole count. Hence the next design will use the ATF1508AS in PLCC84, which will give me 64 uncommitted I/O pins and quite a bit more flexibility. There's also a TQFP100 version of the 1508, offering even more pins in a slightly smaller package, but soldering one of those is out of the question for me.

You should keep all this in mind when you do your next design, since you may determine later in the design cycle that you want to add more capability to the CPLD logic, but don't want to be forced into accepting whatever pin layout the fitter determines for you. Best to go big and avoid having to use every pin. Also, don't forget the JTAG port so you can reprogram your CPLD in-system.

Quote:

3- Provide additional logic for a NMI trigger
- My monitor supports a NMI panic routine, so having a way to invoke it would be nice

If the only use of NMI will be via a "panic button", which is the case in my POC units, you can dampen NMI with a Maxim DS1813, which is in a TO92 package, and thus quite space-thrifty.

Quote:

4- Likely a 4-layer board for better shielding and higher clock speeds

Use of a four-layer board was something I chose from the very beginning. Aside from the electrical benefits, your design can be denser because you don't need to consume real estate in routing power and ground. The cost of getting four-layer boards made has come down quite a bit in the last 10 years and I would never consider going back to two layers for digital work.

Quote:

5- Onboard serial console via a USB connector
- Power switch w/center off allowing power select from USB or dedicated connector

Not sure if powering your project from a USB port would be a good idea. My experience is the available power is a bit weak, and regulation sometimes isn't all that great. At a minimum, I would use a wall-wart with 9 to 12 volts DC output and regulate it to Vcc on your board.

I use an old 250 watt ATX PC power supply to run my projects. There's enough juice to power POC plus any disks attached to it. You just have to be a little careful when powering up a brand new design with a PC power supply, as it can produce some pretty high short circuit currents before cutting itself off. For example, a backwards electrolytic will go with quite a bang.

Quote:

I'm using the machined IC sockets from Mill-Max and can easily insert a ZIF connector into the ROM socket which makes removing the EEPROM quick and easy. I prefer not to solder these to the board as they are expensive and can easily be reused for other projects down the road.

I used a similar type of socket on POC V2.0 for the ROM and expansion port, made by CNC Tech, their part number 210-1-28-006. The ROM is plugged into an Aries part number 28-6554-11 ZIF socket, which can be safely plugged into the DIP socket.

[BigDumbDinosaur]

cbmeeks wrote:

BigDumbDinosaur wrote:

Np, no, NO! You will ruin the socket into which you have plugged the WW socket.

The socket that I used for the ROM cost about $0.12 and I have dozens of them.

I'm not thinking of the purchase price of the socket, but the pain of extricating the damaged one from the board.

[floobydust]

BigDumbDinosaur wrote:

floobydust wrote:

If I were to do this again, I would do it a bit differently;
1- A different pinout for the I/O connector making it more flexible for using other I/O devices
- 32-bytes wide (rather than 16-bytes)
- Positive going Reset line
- Cleaner signal distribution on the 30-pin connector

A low going reset should still be present for maximum flexibility.

Also, more related to construction than design, ideally each signal in the cable should be separated from the next signal by a ground. In other words, ground -- signal -- ground -- signal --, etc. This is a technique seen in some disk drive cables (the single-ended SCSI bus, for example) the helps to reduce crosstalk.

Quote:

2- Use a CPLD for glue logic so I can alter the ROM/RAM-I/O addressing

Not only does that give you some flexibility in overall design, it opens the door to adding features that aren't very practical with discrete logic, such as different memory map combinations.

One of the limitations of my POC V2 design is I opted to use Atmel's (now Microchip's) small ATF1504AS CPLD, which is PLCC44. That decision was based upon the desire to keep my PCB size within the Express PCB Proto-Pro size and hole count limits. As a single PLCC socket can add quite a few holes, I went with the smallest available, which was the PLCC44.

While the 1504 has ample logic resources (64 macrocells), it only has 32 uncommitted I/O pins, which proved to be significant as the design evolved. Every pin is in use and I had to allow the fitter to automatically choose all pin assignments except for the clock and reset inputs. As you could imagine, this added complication to laying out the PCB, since I couldn't use a "best fit" methodology to decide how to route the board. As I am using a different source at this time for POC boards, I'm less constrained with the size and hole count. Hence the next design will use the ATF1508AS in PLCC84, which will give me 64 uncommitted I/O pins and quite a bit more flexibility. There's also a TQFP100 version of the 1508, offering even more pins in a slightly smaller package, but soldering one of those is out of the question for me.

You should keep all this in mind when you do your next design, since you may determine later in the design cycle that you want to add more capability to the CPLD logic, but don't want to be forced into accepting whatever pin layout the fitter determines for you. Best to go big and avoid having to use every pin. Also, don't forget the JTAG port so you can reprogram your CPLD in-system.

Quote:

3- Provide additional logic for a NMI trigger
- My monitor supports a NMI panic routine, so having a way to invoke it would be nice

If the only use of NMI will be via a "panic button", which is the case in my POC units, you can dampen NMI with a Maxim DS1813, which is in a TO92 package, and thus quite space-thrifty.

Quote:

4- Likely a 4-layer board for better shielding and higher clock speeds

Use of a four-layer board was something I chose from the very beginning. Aside from the electrical benefits, your design can be denser because you don't need to consume real estate in routing power and ground. The cost of getting four-layer boards made has come down quite a bit in the last 10 years and I would never consider going back to two layers for digital work.

Quote:

5- Onboard serial console via a USB connector
- Power switch w/center off allowing power select from USB or dedicated connector

Not sure if powering your project from a USB port would be a good idea. My experience is the available power is a bit weak, and regulation sometimes isn't all that great. At a minimum, I would use a wall-wart with 9 to 12 volts DC output and regulate it to Vcc on your board.

I use an old 250 watt ATX PC power supply to run my projects. There's enough juice to power POC plus any disks attached to it. You just have to be a little careful when powering up a brand new design with a PC power supply, as it can produce some pretty high short circuit currents before cutting itself off. For example, a backwards electrolytic will go with quite a bang.

Quote:

I'm using the machined IC sockets from Mill-Max and can easily insert a ZIF connector into the ROM socket which makes removing the EEPROM quick and easy. I prefer not to solder these to the board as they are expensive and can easily be reused for other projects down the road.

I used a similar type of socket on POC V2.0 for the ROM and expansion port, made by CNC Tech, their part number 210-1-28-006. The ROM is plugged into an Aries part number 28-6554-11 ZIF socket, which can be safely plugged into the DIP socket.

Hi BDD,

Yes, pretty much what I'm thinking, as I already have the new design mostly completed. I'm adding a positive going reset and keeping the negative going reset as well. As I'm switching over to the NXP UART, having the positive going reset is required. The new design also has the DS1813 for de-bouncing the NMI trigger. I replaced the DS1813 (for the negative going reset) with a RCA TL7705 which gives me both positive/negative with open collector drives. As this is still a simple 65C02 design and pocket-sized, high current is not needed from the power supply. Agreed on the USB power being a bit unreliable, but due to the small size it becomes an option via a FTDI interface to the UART. The CPLD I'm working with the is the AT750CL, which, depending on your POV, isn't much of a CPLD but a 22V10 on slight steroids

The AT750CL will provide the on-board ROM/RAM/UART selects, the four I/O selects on the buss connector and the MRW/MRD lines for memory and UART access.

Still, this makes for a tiny board, low current consumption, reasonable function and expandable. The 30-pin buss connector will be a simple layout sans the additional ground lines (agree on shield/ground lines ala SCSI) but the current buss layout is surviving 10MHz with a 2-inch ribbon cable. Pin-out is pretty simple:
8- data lines
5- address lines
4- I/O selects
9- pins for MRD, MWR, R/W, RES, RES/, CLK, SO, IRQ, NMI
4- pins for power, 2@Gnd and 2@+5V
The pinout allows the connector to be reversed (accidentally) without smoking anything as the Gnd lines are centered and the +5V is on the ends. Clock rate will be spec'd at 8MHz which should be okay for many things with the 8-bit 65C02. Again, this is a small and simple board which can be functional with a console and timer support solo and the ability to reasonably expand to a point.

I'm also using the ExpressPCB for the boards, which is why I have 3 board sets of the original design

PS - interested to see how your new POC V2 works out

[BigDumbDinosaur]

floobydust wrote:

The CPLD I'm working with the is the AT750CL, which, depending on your POV, isn't much of a CPLD but a 22V10 on slight steroids

The ATF750C is classified as an SPLD, not a CPLD, so it is indeed a GAL on steroids. Note that the 750C has no JTAG port, which eliminates in-circuit programming from the picture. I only know of two companies who make compatible programmers, and they aren't cheap.

The 750C has no more I/O than a 22V10, only more logic (include flops). Also, compared to the ATF1504AS, which is a true CPLD, your ability to do buried logic in the 750C is limited, which means you may find yourself using one or more pins as nodes in some cases. Doing so decreases the available I/O capacity and increases propagation time in any logic that involves a node, as prop time is rated pin-to-pin. I briefly looked at the larger ATF2500C during the early stages of designing POC V2 and set aside precisely for that reason.

I'd think very carefully about this choice before committing to it.

Quote:

I'm also using the ExpressPCB for the boards, which is why I have 3 board sets of the original design

When you get your schematic and PCB layouts all worked out you can copy me on the files and I can run them through the checker for you to weed out any errors. Saves a ton of time and keeps you from paying EPCB to make defective boards for you.

Quote:

PS - interested to see how your new POC V2 works out

It should be. The twin DUART setup slightly complicates the firmware, since the two devices are separated by $0100 in the I/O map. So the code has to behave a little differently. However, the technique of using (<dp>,X) addressing to select DUART registers according to which channel is be read or written has been tested in POC V1.1 at 15 MHz, using a 45ns OTP ROM. I expect a lot less grief with getting serial I/O up and running this time.

[floobydust]

BigDumbDinosaur wrote:

floobydust wrote:

The CPLD I'm working with the is the AT750CL, which, depending on your POV, isn't much of a CPLD but a 22V10 on slight steroids

The ATF750C is classified as an SPLD, not a CPLD, so it is indeed a GAL on steroids. Note that the 750C has no JTAG port, which eliminates in-circuit programming from the picture. I only know of two companies who make compatible programmers, and they aren't cheap.

The 750C has no more I/O than a 22V10, only more logic (include flops). Also, compared to the ATF1504AS, which is a true CPLD, your ability to do buried logic in the 750C is limited, which means you may find yourself using one or more pins as nodes in some cases. Doing so decreases the available I/O capacity and increases propagation time in any logic that involves a node, as prop time is rated pin-to-pin. I briefly looked at the larger ATF2500C during the early stages of designing POC V2 and set aside precisely for that reason.

I'd think very carefully about this choice before committing to it.

Quote:

I'm also using the ExpressPCB for the boards, which is why I have 3 board sets of the original design

When you get your schematic and PCB layouts all worked out you can copy me on the files and I can run them through the checker for you to weed out any errors. Saves a ton of time and keeps you from paying EPCB to make defective boards for you.

Quote:

PS - interested to see how your new POC V2 works out

It should be. The twin DUART setup slightly complicates the firmware, since the two devices are separated by $0100 in the I/O map. So the code has to behave a little differently. However, the technique of using (<dp>,X) addressing to select DUART registers according to which channel is be read or written has been tested in POC V1.1 at 15 MHz, using a 45ns OTP ROM. I expect a lot less grief with getting serial I/O up and running this time.

I agree that the ATF750 isn't truly a CPLD, but Atmel (now Microchip) still list it as one, who knew. As my requirements are pretty meager, being memory and I/O decode plus generating qualified read/write, it should be able to do this. It's a similar application to Daryl's 22V10 decode chip. While it doesn't have a JTAG port, I don't need that as my programmer (Dataman 40Pro) claims to support a pretty large list of Atmel chips, this one included.

ExpressPCB, thanks very much for this offer, very kind of you. It will be a little while on the board layout still... as I need to get an ATF750 programmed and verified and the BIOS code written for the NXP UART. I'll use a protoboard or an adapter to get those pieces working with my existing boards first.

POC V2 - I watch the thread... so will follow your progress on this new board. I know you've been using either older EPROMs or OTP ROMs which are rated fairly quick. I opted for an EEPROM with insitu programming. I'm finding the Atmel EEPROMs to be quite conservatively rated. I have a tube of their 150ns 32KB (AT28C256-15PU) chips and I'm running the board set at 10Mhz for years now. I also have some of their 70ns rated chips in PLCC and will try one of these in an adapter to see if I can push it a bit further. While it's not a desirable long term plan, they have been fully reliable at higher speeds.

[Arlet]

Quote:

I'm not thinking of the purchase price of the socket, but the pain of extricating the damaged one from the board.

If you don't care about reusing the socket, a simple trick is to heat each pin until the plastic around the pin melts, and then pull it out.

[cbmeeks]

Arlet wrote:

Quote:

I'm not thinking of the purchase price of the socket, but the pain of extricating the damaged one from the board.

If you don't care about reusing the socket, a simple trick it to heat each pin until the plastic around the pin melts, and then pull it out.

That's a neat idea.

However, I have a de-soldering pump so it shouldn't be too hard removing that socket. I just need to decide if it's worth it or should I just chunk it and move on to my next project.

I've got another project that is a mixture of wire-wrapping and soldering on a much larger board. I'm using nice thick lines for power/ground and soldering the caps to the sockets.

What I really need to do is print out the reversed pinouts of each chip and put them next to the socket. I keep having to flip the board over and over to see where I'm at.