Unloaded clock signal pic

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Dan Moos
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Unloaded clock signal pic

Post by Dan Moos »

This is my clock signal. The setup is simple. Oscillator on breadboard, probing output. Clock not hooked to anything, so the only load is 1M/13pF of my scope probe.

On the bottom of the screen are measurements I thought might be relevant. Not show is the rise time, which measured at 2.6ns.


First off, if nothig changes, this should work fine, right?

Second, I assume once in circuit, since we are dealing with CMOS, it shouldn't be significantly loaded, right? As in, my scope probe is the biggest load it will see?

Third, if that ringing is a big deal, could I not put a resistor to ground at the output to dampen it.Actually, experimentation with a 500 ohm load didn't change the ringing much, just the amplitude. That load should have been drawing 10 mA, which is about 2/3 the rating of the part. Thus, I doubt there are any gains to be made here.

Finally, can I expect this to change when the oscillator is in-circuit?
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GARTHWILSON
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Re: Unloaded clock signal pic

Post by GARTHWILSON »

You could put a monolithic ceramic one across the power though, with shortest possible leads & connections to the power and ground leads of the oscillator can. Then, make the connections (both output and ground) from there directly to the processor's Φ0 in and ground as short as practical, and from the processor to the VIA's and ACIA's Φ2 input also short. Processor first though. Then you can 'scope it at the processor, including using the processor's ground pin. You'll probably find it doesn't look so nice out there as it does right at the oscillator's output. Part of the problem is that the wire's inductance is about 24nH per inch (that's for #24 wire, but going to a larger gauge has a pretty negligible effect), and there are capacitive loads out at the end of it (from the solderless breadboard and the input capacitance of the ICs), a situation that's ripe for ringing. When possible, keeping the signal line right next to its corresponding ground return wire helps.
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BigDumbDinosaur
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Re: Unloaded clock signal pic

Post by BigDumbDinosaur »

Dan Moos wrote:
This is my clock signal.
The ringing when the clock is high isn't something about which to be terribly concerned, as it appears to not dip down below what is a safe minimum. What you should investigate is that significant undershoot when the clock goes low. You may be seeing ground bounce at the oscillator.

BTW, when you were testing did you have the 'scope probe on the ×10 setting, and the probe's ground attached to the oscillator's ground?
Quote:
Second, I assume once in circuit, since we are dealing with CMOS, it shouldn't be significantly loaded, right? As in, my scope probe is the biggest load it will see?
The individual CMOS devices won't be your concern. It will be the wiring itself where the big losses will occur. Unfortunately, those losses will rapidly increase as a function of frequency (see below).
Quote:
Third, if that ringing is a big deal, could I not put a resistor to ground at the output to dampen it.Actually, experimentation with a 500 ohm load didn't change the ringing much, just the amplitude. That load should have been drawing 10 mA, which is about 2/3 the rating of the part. Thus, I doubt there are any gains to be made here.
A lower resistance might help but will also load the oscillator more, possibly dragging down the maximum amplitude of the clock signal. Thevenin termination is another possibility, but is not a simple thing to work out.
Quote:
Finally, can I expect this to change when the oscillator is in-circuit?
Garth covered that in his reply. Breadboards are not a friendly environment to digital signals. Said signals have very strong odd-order harmonics that ultimately determine just how "square" the square wave will be. Anything that drags down high frequencies in some way will cause the signal to deviate from the ideal square wave. If that deviation is sufficiently severe the circuit will be unstable or DOA.
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Dan Moos
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Re: Unloaded clock signal pic

Post by Dan Moos »

My probes were exactly as you described BDD.

Why is the undershoot a bigger deal than the over shoot? Both are roughly a volt, so I'm apparently going negative by a volt (scope says this). It's that bad?

But to get to the nub if of it, conceding that yes, a breadboard is a terrible environment for digital, does anything I've so far posted suggest things won't work? I've seen some pretty messy functional computers on breadboards on the net.

If I decide to do a long term build, it will be PCB, probably home brewed (I'm getting dangerously close to the getting kinds of results that would allow it using the photo technique)
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BigDumbDinosaur
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Re: Unloaded clock signal pic

Post by BigDumbDinosaur »

Dan Moos wrote:
Why is the undershoot a bigger deal than the over shoot? Both are roughly a volt, so I'm apparently going negative by a volt (scope says this). It's that bad?
A volt is a lot. The WDC specs for the 65C02 say that absolute maximum rating for any input (the clock is an input) is -0.3 to Vdd+0.3. The behavior of the device is undefined if any input goes more than 0.3 volts below ground, and while nothing in the data sheet suggest that the brief undershoot you are seeing will be fatal, you are wading into uncharted waters.

You need to see if you can reduce that undershoot if you can. Running the clock through a flop may help.
Quote:
But to get to the nub if of it, conceding that yes, a breadboard is a terrible environment for digital, does anything I've so far posted suggest things won't work? I've seen some pretty messy functional computers on breadboards on the net.
So far I don't see any showstoppers. However, the star topology for the buses may give you some grief.
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If I decide to do a long term build, it will be PCB, probably home brewed (I'm getting dangerously close to the getting kinds of results that would allow it using the photo technique)
The ideal is to build on a four-layer PCB, with power and ground on the inner layers. The gain in noise and ground bounce control is considerable. I built both of my POC designs on a four-layer board, and achieved 15 MHz operation on POC V1.1. Fabricating a four-layer board at home would be a...er...challenging task. :)
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GARTHWILSON
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Re: Unloaded clock signal pic

Post by GARTHWILSON »

Regarding the solderless breadboard, I expect it will work as long as you heed earlier advice.

Regarding PC boards, know that the price of getting a custom board made by a board house has come well within the reach of hobbyists, much to our delight. There's discussion of it in chapter 13 of the 6502 primer, with links. See also our forum topic, "Cheap PCB stories..." It started more than five years ago, so you'll see progress as the topic goes from one page to the next, to the next.
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Arlet
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Re: Unloaded clock signal pic

Post by Arlet »

Dan Moos wrote:
This is my clock signal. The setup is simple. Oscillator on breadboard, probing output. Clock not hooked to anything, so the only load is 1M/13pF of my scope probe.
How close is the scope probe and ground clip to the oscillator ? Try to measure real close and far away to see the difference. Also, if this is a canned oscillator, try taking it out of the breadboard, and attach power and scope directly, to see if there's a difference.

In general, if you want to get a good look at a signal, make sure the ground clip is attached close to that signal.

If you want to soften the edges a bit, try adding a resistor in series with the output. Something between 22 and 220 Ohms should probably work.
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BigEd
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Re: Unloaded clock signal pic

Post by BigEd »

(I read a howto guide the other day, pointing out that you need to periodically recalibrate your probes - they have circuitry which compensates for their impedance, and if misadjusted can show you things which are not really there in normal operation.)
Martin A
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Re: Unloaded clock signal pic

Post by Martin A »

I happen to be in the process of putting together something with a 2mhz clock using matrix board. So I've powered up the clock to get a shot of the waveform.

It's a 5v can oscillator, and there's a 0.1uf smoothing capacitor between 5v and ground, and no load other than the wire from the output to the various IC sockets. Other than a power indicator LED there's nothing else currently fitted.

The under and overshoot are very similar, though the ringing does appear to dissipate faster, I don't know if that's the result of the capacitor or being on matrix board rather than a breadboard.
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BigDumbDinosaur
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Re: Unloaded clock signal pic

Post by BigDumbDinosaur »

BigEd wrote:
(I read a howto guide the other day, pointing out that you need to periodically recalibrate your probes - they have circuitry which compensates for their impedance, and if misadjusted can show you things which are not really there in normal operation.)
Good observation! The instructions that came with the probes I use tell you to periodically check calibration.
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