Dan Moos wrote:
This is my clock signal.
The ringing when the clock is high isn't something about which to be terribly concerned, as it appears to not dip down below what is a safe minimum. What you should investigate is that significant undershoot when the clock goes low. You may be seeing ground bounce at the oscillator.
BTW, when you were testing did you have the 'scope probe on the ×10 setting, and the probe's ground attached to the oscillator's ground?
Quote:
Second, I assume once in circuit, since we are dealing with CMOS, it shouldn't be significantly loaded, right? As in, my scope probe is the biggest load it will see?
The individual CMOS devices won't be your concern. It will be the wiring itself where the big losses will occur. Unfortunately, those losses will rapidly increase as a function of frequency (see below).
Quote:
Third, if that ringing is a big deal, could I not put a resistor to ground at the output to dampen it.Actually, experimentation with a 500 ohm load didn't change the ringing much, just the amplitude. That load should have been drawing 10 mA, which is about 2/3 the rating of the part. Thus, I doubt there are any gains to be made here.
A lower resistance
might help but will also load the oscillator more, possibly dragging down the maximum amplitude of the clock signal. Thevenin termination is another possibility, but is not a simple thing to work out.
Quote:
Finally, can I expect this to change when the oscillator is in-circuit?
Garth covered that in his reply. Breadboards are not a friendly environment to digital signals. Said signals have very strong odd-order harmonics that ultimately determine just how "square" the square wave will be. Anything that drags down high frequencies in some way will cause the signal to deviate from the ideal square wave. If that deviation is sufficiently severe the circuit will be unstable or DOA.