I think I finally have my decoding down. Suggestions needed.

[GARTHWILSON]

Don't use LS. Its inputs load the signal lines a lot more, and its outputs can't pull up high enough for some CMOS loads to recognize them consistently as a valid "1".

[cbscpe]

Yes, as Garth said, stay with a CMOS only design if possible. HC is fast enough for a 4MHz system. AC is required for faster systems only.

[BigDumbDinosaur]

cbmeeks wrote:

I'm going to order some AC series logic. But I'm assuming LS would be fine for 1-2 MHz systems?

Avoid 74LS in new designs. That's like using tires from the 1940s on a new automobile.

[cbscpe]

Hi cbmeeks,

here the schema for the decoder I was referring to in one of my previous posts. I hope you also put some 74AC00 into your basket at mouser.

Minimalistic Decoder for a 6502 System

minimal-decoder.png (7.61 KiB) Viewed 1875 times

cbmeeks wrote:

So the basic principal is that using the 1 of 8 decoder, I get 8 different IO devices using A[13:11]. But I'm not sure I understand what you mean about the 65XX sharing IO lines. I'm thinking 8 IO devices is plenty (up from my original 6). Or, do you mean something else?

A typcial 65xx peripheral has two chip selects, one is active low and the other active high. Both must be asserted for the chip to be selected. In case of a W65C22S these are named CS1 and /CS2 (respectively C2B). When CS1 is high and /CS2 is low the W65C22 is selected. Now lets assume that you have 4 (or more) W65C22S. Then you can connect all /CS2 to one of the outputs of the 74HC138, in our case lets use /Y0 which is asserted for $8000..$87FF. Now you connect A4 to CS1 of the first W65C22, A5 to the CS1 of the second W65C22, A6 to the CS1 of the third W65C22 and A7 to the CS1 of the forth W65C22. Now when accessing a address in the range $8010..$801F CS1 of the first W65C22 is high and CS1 of the others W65C22 is low, so only the first W65C22 is selected. The same happens when using any address in the range of $8020..$802F for the second, $8040..$804F for the third and $8080..$808F for the forth W65C22. Of course you should avoid all addresses with more then one of the address lines A4, A5, A6 and A7 set to one. Especially on reads. In this way using only one chip select from the address decoder you can select multiple 65xx devices. And they don't have to be all the same type.

[Michael]

cbscpe wrote:

Hi Micheal, I would rather not use the '139 to create the PHI2 qualified signals as the '139 is rather slow compared to a 74AC00 and due to the very short data hold time provided by the W65C02 and the required data hold time of normal speed RAM (55ns or slower) this could violate the guaranteed times for writes

Hi Peter.

Looking at the TI Datasheets for 74AC00 and 74AC139, the propagation times at 3.3 volts seem pretty close. Perhaps you or another forum member could point out why using a 74AC139 in this application might be a problem, please?

TIA... Cheerful regards, Mike

[cbscpe]

Right you are the difference in prop delay for the AC versions are extremely small. I must admit that this was based on the figures I had in mind for the other technolgies (HC, LS, etc.). So yes the '139 would be a feasable single chip option.

[cbmeeks]

Michael wrote:

A couple single chip solutions come to mind;

decoder 1.png

Michael,

I really like the idea of a simple one-chip decoder. When looking at your schematic, are you saying that I would pick either the left or right and not both?

Would you mind letting me know the pros/cons of either one?

Thanks

[Michael]

cbmeeks wrote:

I really like the idea of a simple one-chip decoder. When looking at your schematic, are you saying that I would pick either the left or right and not both?

That's correct. You would choose either the ɸ2 Qualified RD/WR or the ɸ2 Qualified RAM Select circuit.

A third method involves driving the active-high chip select pin available on 8K, 64K, or 128K SRAM chips directly from the ɸ2 clock. The active-low chip select from the address decoder (the A15 address line in this case) would drive the SRAM active-low /CS and /OE pins while the 65C02 R/W line drives the SRAM /WE pin.

Speaking of single-chip solutions, Daryl Rictor (8BIT) has a very nice 22V10 Memory Decoder GAL available.

Quote:

Would you mind letting me know the pros/cons of either one?

That's pretty much the same question I asked earlier. We see both methods used all the time. I'd really like to hear the conclusions and (qualified) opinions from our more experienced and knowledgeable members.

Cheerful regards, Mike

[cbscpe]

For moderate clock rates and decent RAM access times it does not matter. What I mean is that if the PHI2 high phase is longer than the sum of the delay time of the decoder, the '139 in this case, plus the access time of the RAM, plus the data set up time of the CPU, plus any delays of bus drivers if included, you can use a signal controlled by PHI2 to control the chip selects of the RAM. However in case the PHI2 high phase is longer than the sum you should consider a setup that creates the chip selects as early as possible. The reason is that many high speed RAM use the chip select to activate the address decoder and the access time from chip select to valid data is higher than the delay from output enable to valid data. This is because the RAM chips put the address decoder into a power save mode when the chip is not selected to save power. For systems with 32kbyte RAM I always use A15 as the chip select. Then also many non 65xx peripherals require a RD and WR signal that is asserted after the chip selects are asserted. Having a global RD and WR qualified with PHI2 then can not only be used to control OE and WE of the memory but as well be used for these peripherals.

[cbmeeks]

@Michael

So, going by your example...if I used the scenario on the left (qualified by /RD, /WR), what prevents me from reading from ROM and RAM at the same time? What disables the RAM chip?

[Michael]

cbmeeks wrote:

@Michael

So, going by your example...if I used the scenario on the left (qualified by /RD, /WR), what prevents me from reading from ROM and RAM at the same time? What disables the RAM chip?

The A15 address line is used for the SRAM active-low chip enable ($0000-$7FFF) while the /ROM decoder output is used for the ROM active-low chip enable ($C000-$FFFF).

[cbmeeks]

Ah, OK. That was the piece I was missing. A15 goes into the /CE of RAM AND the '139 mux.

While I admit I'm an uber n00b when it comes to this stuff, I can't find anything wrong with the design and I think it would be a great fit for what I want to build.

I plan on using a couple Propellers instead of the ACIA but I should be able to treat them like any other I/O device.

Thanks

[Michael]

Just came across an interesting '139 decoder circuit. It appears to avoid bus contention if you were to accidentally write to an address in EPROM. What's interesting to me is the use of the PHI1 output instead of the PHI2 output and the use of a 74139 decoder. Is there such a thing as a 74139?

Does anyone know if there is an advantage using PHI1 instead of PHI2 to qualify the Read/Write signals in this decoder design? Also, why the extra inverter going to the B input on the second half of the 74139? Couldn't it be eliminated by simply moving some decoder outputs?

Regards, Mike

[GARTHWILSON]

Yes, there's a 74139. Use at least an 'HC139 though, or for faster designs, an 'AC139.

Phase 2 is basically phase 1 after an inverter, used here since the '139 has a negative logic "Gate" input but not a positive logic one. There will be a few ns delay from phase 1's edge to phase 2's, but not enough to cause any trouble here.

Douglas Beattie is very sharp; but we all overlook possibilities sometimes, and it does look like you could eliminate that one inverter section if you swap that 139's Y0 and Y2 outputs and swap its Y1 and Y3 outputs.

[BigDumbDinosaur]

Also, the simultaneous assertion of /CE and /OE on the EPROM will have some negative effects on performance.

It's best if /CE is asserted as soon as the address bus goes valid with an EPROM address, even though Ø2 is still low. /OE should only be asserted when Ø2 goes high. Controlling both inputs from a single source, as shown in the above circuit, narrows the window of opportunity to read the EPROM before the end of the bus cycle. This because it takes time for the EPROM to come out of the high-Z state and connect to the bus, which can only occur when both /CE and /OE have been asserted. Asserting /CE is what "wakes up" the device from low power mode and typically takes the most time. Hence the suggestion that /CE be asserted as soon as a valid address exists. Reading the device should be gated only with /OE.