We know that datasheets dictate timing in terms of pulse-width, not duty cycle, so in that sense we can choose any duty cycle we please as long as pulse-width spec's are satisfied. The linked Commodore datasheet
is a bit of a headscratcher, though!
I quickly noticed two typos, and later a couple of goofy but serious problems I won't bother describing unless someone asks. Also, regarding the point at hand, I find it odd that Commodore lists both min
and max figures for PWHØ0 (ie, Ø0 (IN) Pulse Width).
Rockwell's NMOS '02 datasheet makes more sense, specifing a min figure only, as I'd expect. (Both datasheets state a limit for slowest operation, but they do so by means of a separate spec -- either min clock frequency or its reciprocal, max cycle time.)
Attachment:
Rockwell NMOS '02 timing.png [ 62.56 KiB | Viewed 527 times ]
Here (above) is what Rockwell has to say, and I must say I sure as heck would rather use their datasheet than Commodore's!! I expect the two chips are fundamentally the same, even though the exact figures may differ. It looks to me as though it's possible to stop the clock either high or low for periods up to about 10 uS (Rockwell) or 20 uS (Commodore). The actual (as opposed to specified) limit may be in the millisecond range, as Ed suggested.
I agree the 'C02 offers even more timing freedom (and other major advantages as well). But you can go a long way with 10 uS -- certainly in terms of cycle-stretching, and even DMA.
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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