Reason why 6502 ignores RDY during write cycles?

[Arlet]

So, in theory somebody could make a design where the clock is stopped for somewhat less than 20 microseconds, and then do a single 'refresh' cycle. If they really wanted to use the NMOS part, of course.

[BigEd]

I think that would work. It might not suit a life-critical application!

[Tor]

BigDumbDinosaur wrote:

That's because there is no delete button. Everyone knows that once it's on the Internet it never goes away.

I wish that were true, sometimes.. see "The secret, hidden, transparent 6502 DMA channel" (the illustrations are gone.)
(I'm currently hunting another info page which disappeared with no trace in archive.org or anywhere else. With little hope)

[BigDumbDinosaur]

Tor wrote:

BigDumbDinosaur wrote:

That's because there is no delete button. Everyone knows that once it's on the Internet it never goes away.

I wish that were true, sometimes.. see "The secret, hidden, transparent 6502 DMA channel" (the illustrations are gone.)
(I'm currently hunting another info page which disappeared with no trace in archive.org or anywhere else. With little hope)

I, of course, was being somewhat sarcastic. As you've noted, things do seem to disappear now and then. It's the embarrassing stuff that seems to stick around.

[GARTHWILSON]

BigEd wrote:

Ah, I see 50kHz minimum is mentioned on a datasheet. That gives a max cycle time.
http://archive.6502.org/datasheets/mos_ ... v_1985.pdf
via viewtopic.php?f=4&t=3371

and

Quote:

So, in theory somebody could make a design where the clock is stopped for somewhat less than 20 microseconds, and then do a single 'refresh' cycle. If they really wanted to use the NMOS part, of course.

The data sheet is not clear on whether the duty cycle must be 50% at the minimum guaranteed operating frequency; but if it does need to, you would need to have a clock edge at least every 10µs, which is the half cycle.

[Dr Jefyll]

We know that datasheets dictate timing in terms of pulse-width, not duty cycle, so in that sense we can choose any duty cycle we please as long as pulse-width spec's are satisfied. The linked Commodore datasheet is a bit of a headscratcher, though! I quickly noticed two typos, and later a couple of goofy but serious problems I won't bother describing unless someone asks. Also, regarding the point at hand, I find it odd that Commodore lists both min and max figures for PWHØ0 (ie, Ø0 (IN) Pulse Width).

Rockwell's NMOS '02 datasheet makes more sense, specifing a min figure only, as I'd expect. (Both datasheets state a limit for slowest operation, but they do so by means of a separate spec -- either min clock frequency or its reciprocal, max cycle time.)

Here (above) is what Rockwell has to say, and I must say I sure as heck would rather use their datasheet than Commodore's!! I expect the two chips are fundamentally the same, even though the exact figures may differ. It looks to me as though it's possible to stop the clock either high or low for periods up to about 10 uS (Rockwell) or 20 uS (Commodore). The actual (as opposed to specified) limit may be in the millisecond range, as Ed suggested.

I agree the 'C02 offers even more timing freedom (and other major advantages as well). But you can go a long way with 10 uS -- certainly in terms of cycle-stretching, and even DMA.

-- Jeff

[cbmeeks]

Concerning the Apple IIe and stopping the clock...

I could be wrong but I'm pretty sure the Apple IIe (or II series) did not stop the clock even while rendering video.

IIRC, the video hardware would access the addr/data bus during the low phase of the cycle and the CPU gets it during the high phase. Or something like that. Effectively allowing both devices to access data at the same time. Well, same clock time.

At least that's how I understand it works

[barrym95838]

cbmeeks wrote:

... I could be wrong but I'm pretty sure the Apple IIe (or II series) did not stop the clock even while rendering video ...

Apparently it wasn't a stop, but more of a periodic stretch:

viewtopic.php?p=29095#p29095

Mike B.

[BigEd]

As RDY was brought to the internal expansion bus, it's possible that some Apple I/O cards would use RDY to stall the CPU while they did some DMA. As you say, the clock itself continues, in its special irregular way. But the programmer experience could be that the CPU stops for DMA.