How do we handle the loss of 5V CPLDs?

[Dr Jefyll]

BigEd wrote:

Well, it does make them supply-voltage compatible, but as you have to drop the supply voltage you will lose clock speed - unless you have suitable level conversion in place.

cr1901 wrote:

Million-dollar question: How much propagation delay do these level shifters add?

Interestingly, some of the level conversion chips (like the 74cb3t3384 I linked to above) offer essentially zero propagation delay. That's because the device is a transmission gate, and current can travel right through it. IOW the signal isn't buffered or amplified; it actually conducts through the device. It behaves basically as a 5 ohm resistor (except when tri-stated). I'm not sure I understand how the level shift aspect works -- is it acting as a Source Follower? Bi-directional, no less?? -- but I expect some of our members understand the fine points of FETs better than I. Meanwhile the datasheet tells me how to use it, and I'm comfortable with that.

-- Jeff

[scotws]

GARTHWILSON wrote:

I expect it has to do with the fact that the WDC parts can run down to 1.2V, unlike 74HCTxx which is 5V only.

This might be one of my Somewhat Stupid Noob Questions (TM), but for the long term, shouldn't we be looking at how to move our designs to 3.3V instead of hanging on to 5V?

[BigDumbDinosaur]

scotws wrote:

GARTHWILSON wrote:

I expect it has to do with the fact that the WDC parts can run down to 1.2V, unlike 74HCTxx which is 5V only.

This might be one of my Somewhat Stupid Noob Questions (TM), but for the long term, shouldn't we be looking at how to move our designs to 3.3V instead of hanging on to 5V?

I've resisted it because so many I/O devices are 5 volts. Also, as you reduce the voltage, the maximum rate at which CMOS devices can be run is likewise reduced. So there are compelling reasons to try to stay with 5 volts.

[Dr Jefyll]

scotws wrote:

shouldn't we be looking at how to move our designs to 3.3V instead of hanging on to 5V?

Yes. But, like BDD, I'm less than eager to embrace 3.3V even though the industry trend is toward lower voltages. As a 65xx fan, I have reason to wish things would just stay the same (ie, 5 volt). But I think we'd have less interest in how the handle the loss of 5V CPLDs if 65xx micros were being made in a process optimized for 3.3V.

BigDumbDinosaur wrote:

as you reduce the voltage, the maximum rate at which CMOS devices can be run is likewise reduced.

True. But to clarify for Scot (who's probably wondering), 3.3V chips running on 3.3 volts don't suffer any performance loss. The problem arises when a system with one power supply includes both 3.3V chips and chips (such as WDC micros) which can accept 3V or 5V. It's not permissible to operate the 3 volt chip on 5V, so instead the 5V-capable chip must run on 3.3 volts -- which means it'll fall short of its potential, performance-wise.

It's unfortunate, because there are some lovely, high-capacity RAMs on the market nowadays, and it'd be feasible to fully populate all 16 megabytes of an 65c816 system! But unless/until the '816 is offered in a new process optimized for 3.3V operation, we're forced to compromise somehow. Level-shifter ICs would allow a dual-voltage system, but that wouldn't completely avoid the problem because level-shifters impact performance, too.

-- Jeff

[Tor]

According to what I'm reading from a commentator over on another forum, 5V parts aren't going away.. the selection is increasing, including new 5V ARM processors. Apparently this has to do with e.g. the automotive industry, or noisy environments etc.

[banedon]

74cb3t3384 seems only to come in SMD .

[GARTHWILSON]

banedon wrote:

74cb3t3384 seems only to come in SMD .

Not a problem, if you can spend $8 or $10 on an adapter to put it in a DIP socket:
http://www.jameco.com/webapp/wcs/stores ... 2130263_-1 :


or http://www.jameco.com/webapp/wcs/stores ... =CAT151PDF :

6502.org wrote:

Image no longer available: http://www.jameco.com/Jameco/Products/M ... 178195.jpg

[banedon]

Thanks Garths. I thought there was some sort of trade off in maximum speed if you use one of these? I.e. one of the reasons for doing wirewrap is to get direct straight connections, but the extra traces on the card inhibit this?

[GARTHWILSON]

True, it's not quite ideal, but the inductance of the connections from the WW pins to the IC's die would not be much different from what it would be using a DIP leadframe plugged into the same socket. Getting a custom board made, with power and ground planes, and soldering SMT parts down to it with no socket, would be better for high-speed performance.

I still find it hard to believe that whoever chose the pinout of 74xx ICs decades ago with the power and ground pins at the corners instead of the middle of each side couldn't look ahead far enough to realize that parts were going to get faster and faster, and that keeping the inductance of the power and ground connections down would become paramount! So bone-headed!

[Windfall]

BigDumbDinosaur wrote:

Also, as you reduce the voltage, the maximum rate at which CMOS devices can be run is likewise reduced.

I wonder if this is always true, and what would cause the effect. Case in point, two of my own designs :

a) http://web.inter.nl.net/users/J.Kortink ... /index.htm
b) http://web.inter.nl.net/users/J.Kortink ... /index.htm

Both use a 14 MHz rated W65C02, although a) can also employ a W65C816. a) is a DIP, runs at 5V, and up to 20 MHz (with 20 ns SRAM). b) is a QFP, runs at 3V3, and up to 24 MHz. Maybe not an exactly 1:1 comparison, but nevertheless there is no indication that at 3V3 the W65C02 suffers from limited clock speed.

[BigDumbDinosaur]

Windfall wrote:

BigDumbDinosaur wrote:

Also, as you reduce the voltage, the maximum rate at which CMOS devices can be run is likewise reduced.

I wonder if this is always true, and what would cause the effect. Case in point, two of my own designs :

a) http://web.inter.nl.net/users/J.Kortink ... /index.htm
b) http://web.inter.nl.net/users/J.Kortink ... /index.htm

Both use a 14 MHz rated W65C02, although a) can also employ a W65C816. a) is a DIP, runs at 5V, and up to 20 MHz (with 20 ns SRAM). b) is a QFP, runs at 3V3, and up to 24 MHz. Maybe not an exactly 1:1 comparison, but nevertheless there is no indication that at 3V3 the W65C02 suffers from limited clock speed.

The W65C02S has been conservatively rated, and the Fmax vs. Vdd curve seems to imply better performance than claimed. However, it tends to be the case that maximum CMOS switching speeds degrade with reduced voltage.

[BigEd]

What John might be seeing is that a QFP is a better package than a DIP for a high speed design. I agree, the physics of CMOS make it slower with reduced voltage - of course, in a complete system there's more going on than the CMOS logic gates in the CPU.

[Dr Jefyll]

GARTHWILSON wrote:

I still find it hard to believe that whoever chose the pinout of 74xx ICs decades ago with the power and ground pins at the corners instead of the middle of each side couldn't look ahead far enough to realize that parts were going to get faster and faster, and that keeping the inductance of the power and ground connections down would become paramount! So bone-headed!

It gets worse. Some of the early TTL chips did have ideally-situated power pins (ie, located toward the middle of the package), but the convention wasn't universal. My (aged and falling-apart) TI TTL databook show several examples from the 5400 series, including the 5400, '01, '02, '04, '05, '10, '11... the list goes on. These 54xx devices had identical function to their 74xx counterparts but Gnd & Vcc were central, not located at either end.

BigDumbDinosaur wrote:

The W65C02S has been conservatively rated

Right -- in that sense we expect the documented figures to be somewhat inaccurate. But (remarking on John's post) when the doc says 5V operation surpasses 3V operation, we expect that comparison to be valid, on the presumption that any conservatism applies equally to both.

Good point about the package, Ed. And John, what was the RAM speed in system (b)?

-- Jeff

[Windfall]

Dr Jefyll wrote:

But (remarking on John's post) when the doc says 5V operation surpasses 3V operation, we expect that comparison to be valid, on the presumption that any conservatism applies equally to both.

Perhaps, under ideal circumstances, 5V powered parts can actually be clocked faster than 3V3 ones. But if 3V3 does 24 MHz, 5V should then do something like 35 MHz. Quite a bit o' overclockin'.

Dr Jefyll wrote:

Good point about the package, Ed. And John, what was the RAM speed in system (b)?

20 ns. If you click on the photo on my website you get a bigger one, and you can see for yourself. Note that the RAM databus goes through the CPLD, but the address bus is direct.

[scotws]

Dr Jefyll wrote:

But to clarify for Scot (who's probably wondering), 3.3V chips running on 3.3 volts don't suffer any performance loss. The problem arises when a system with one power supply includes both 3.3V chips and chips (such as WDC micros) which can accept 3V or 5V. It's not permissible to operate the 3 volt chip on 5V, so instead the 5V-capable chip must run on 3.3 volts -- which means it'll fall short of its potential, performance-wise.

Thanks . What Scot is wondering about now is just how much of a performance hit we are talking about -- reading all of this stuff about 24 and even 35 MHz makes my head swim when I'm wondering about 8 MHz. When does the effect become noticeable?