Hi group,

I have a nice pile of 4168 chips and wanted to use them instead of 6264/4364 SRAMs (they are pin compatible) in a 6502 based subsystem. But I am puzzled with the datasheet.. the chip supposedly should be able to do "auto refresh" but I never used it before and it seems than neither grounding nor pulling up the _RFSH line makes it work. Has anyone of you had some experience with this/similar chip used in place of normal SRAM?

I found something interesting here:

http://www.d81.de/CLD-RAMBOard/RAMBOard-2C.shtml

_RFSH is to be connected to PHI2 and one more cap for delaying the _OE/_CE lines should be added. I did so and it still doesn't work. I even connected CS to PHI2 as in the schematic, although I don't think it to make a difference.

and here:

http://www.smspower.org/uploads/Development/SegaMasterSystemIIServiceManual-1715922A-1.png

This seems to be official schematic from SEGA, which uses the same chip and they do what I did in the first try - connect both CS and _RFSH to VCC.. None of the combinations seem to work for me though.

Any clues, maybe?

Can you share the datasheet with us? (This forum allows attachments to be posted.)

J

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

There's an HTML version here:
http://html.alldatasheet.com/html-pdf/1 ... D4168.html
Edit: and PDF here: http://pdf.datasheetarchive.com/indexer ... 147990.pdf

"The incorporation of an internal refresh address counter and refresh multiplexer allows the user to select one of three refresh modes. The self-refresh mode provides transparent refresh without system overhead. Internal latches for address, data, and chip select allow for use in systems incorporating multiplexed address/data buses."

silverdr:

Two things stand out to me. The first is the diagram provided on page 5 of the datasheet that BigEd liked to. That diagram is likely to provide the reason why the part does not appear to work with either nRFSH tied high or low. A specific set of dummy cycles is required to get the part to initialize after power on: 64 pulses are required on nRFSH and 8 dummy cycles are required on nCE.

The 64 dummy nRFSH cycles need to conform to the basic timing provided in the datasheet above the diagram. That is, 64 pulses must be generated on nRFSH with a nominal rate of 2 ms. These 64 nRFSH pulses can precede or follow, 8 dummy read/write cycles controlled by nCE. The CE-controlled cycle period appears to be about 220/260/330 ns depending on the speed grade of the part will be using.

The second thing that strikes me as critical is that the address must be valid on the following edge of nCE. Thus, in a 6502 system care must be exercised to ensure that the address generated before the rising edge of Phi 2 meets the stated setup and hold times at the part.

I'll let others with personal experience with the NMOS/CMOS 6502 provide more detailed recommendations.

However, from my reading of the datasheet, I would connect ~Phi2 to the part's nCE pin, and I would provide fast address decode to generate CS; it has to be fast because CS must be asserted on the falling edge of nCE in order for the part to recognize the memory cycle. It also appears to me that the late write cycle with nWE generated by gating RnW with Phi2 may be best for a 6502 system.

I might consider providing the nRFSH signal from an nNMI ISR every 2ms. Those routines could also be used to initialize all of the chips installed in your system while your boot code is only running from ROM without any RAM. Once initialized, these devices should work well as your system RAM.

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Michael A.

Here's a thought - if your system happens to access all the rows within a refresh period - whether by running an interrupt or, for example, by fetching video data - it presumably doesn't need to bother with the special refresh mechanism.