// file: clkgen.v
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1_____70______0.000______50.0______346.711____235.738
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clkgen,clk_wiz_v3_3,{component_name=clkgen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module MainCLK
 (// Clock in ports
  input         CLK_IN1,                        //100MHz can oscillator
  // Clock out ports
  output        CLK_OUT1,
  output          CLK_OUT2,
  output          CLK_OUT3,
  output          CLK_OUT4
 );

  // Input buffering
  //------------------------------------
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));


  // Clocking primitive
  //------------------------------------
  // Instantiation of the PLL primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire        clkfbout;
  wire        clkfbout_buf;

  PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (5),                        //100MHz/5 =20MHz*52 = 1040MHz/7 = 148.571MHz for 1920x1080 @60Hz
    .CLKFBOUT_MULT          (52),                     
    .CLKFBOUT_PHASE         (0.000),                  
    .CLKOUT0_DIVIDE         (14),                     //74.25 MHz CPU clk
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKOUT1_DIVIDE         (7),                        //148.5 MHz SyncRAM clk
    .CLKOUT1_PHASE          (0.000),                  
    .CLKOUT1_DUTY_CYCLE     (0.500),
    .CLKOUT2_DIVIDE         (7),                        //148.5 MHz next PVB clk
    .CLKOUT2_PHASE          (0.000),                  
    .CLKOUT2_DUTY_CYCLE     (0.500),
    .CLKOUT3_DIVIDE         (7),                        //148.5 MHz videoDAC clk
    .CLKOUT3_PHASE          (0.000),                  
    .CLKOUT3_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (10.00),
    .REF_JITTER             (0.010))
  pll_base_inst
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1),
    .CLKOUT2               (clkout2),
    .CLKOUT3               (clkout3),
    .CLKOUT4               (),
    .CLKOUT5               (),
    .LOCKED                (),
    .RST                   (1'b0),
     // Input clock control
    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clkin1));
      
  // Output buffering
  //-----------------------------------
  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));

   BUFG clkout2_buf
   (.O   (CLK_OUT2),
    .I   (clkout1));
   
   BUFG clkout3_buf
   (.O   (CLK_OUT3),
    .I   (clkout2));
   
   BUFG clkout4_buf
   (.O   (CLK_OUT4),
    .I   (clkout3));
   
   
endmodule

MainCLK PLL ( .CLK_IN1(MAINCLK1),       //using 100MHz, generate video pixel clock and CPU clock using PLL
                 .CLK_OUT1(clk),            //CPU clock
                 .CLK_OUT2(clk2),         //SyncRAM clock
                 .CLK_OUT3(clk3),         //to next PVB
                 .CLK_OUT4(clk4));         //to videoDAC
   
                     
   ClkOutDDRFF SRCLKOUT ( .SigIn(clk2),       //to SyncRAM   
                          .SigOut(SRCLK));   
                         
   ClkOutDDRFF PCLKOUT ( .SigIn(clk3),       //to next PVB   
                         .SigOut(PCLKout));   
                        
   ClkOutDDRFF VCLKOUT ( .SigIn(clk4),       //to videoDAC   
                         .SigOut(VCLKout));

`timescale 1ns / 1ps

module ClkOutDDRFF (input SigIn,
                    output SigOut
                    );

   ODDR2 #( .INIT(1'b0),                //from the Spartan 6 HDL Library
            .SRTYPE("SYNC"),
            .DDR_ALIGNMENT("NONE") )
            
            inst (.CE(1'b1),
                  .C0(SigIn),
                  .C1(!SigIn),
                  .D0(1'b1),
                  .D1(1'b0),
                  .R(1'b0),
                  .S(1'b0),
                  .Q(SigOut));
endmodule