It will be a wide blockRAM but not too deep. Maybe 8 addresses at this point. The blockRAM databus will be accommodating the required 6-bit address and also 16-bit data going to the pixel generator module. It will be write-only to start, getting it's programming from the 65Org16.b.
After this stage is successful, the 65Org16.b will be removed from each of the PVBs, and then all of them then will receive commands from offboard.
This is why 6-bit address: These are the current registers
Code: Select all
// Register addresses
always @(posedge clk2) //write to registers
if (cpuWE & vgaCS)
case ( cpuAB [5:0] )
6'b000000: x0t <= cpuDO; //variables for line generator
6'b000001: y0t <= cpuDO;
6'b000010: x1t <= cpuDO;
6'b000011: y1t <= cpuDO;
6'b000100: xc <= cpuDO; //variables for circle generator
6'b000101: yc <= cpuDO;
6'b000110: rad <= cpuDO;
6'b000111: color <= cpuDO; //pixel color variable for line/circle/fill/pixel plot
6'b001000: bXlen <= cpuDO; //X length of blitter
6'b001001: bYlen <= cpuDO; //Y length of blitter
6'b001010: bXc <= cpuDO; //X start copy
6'b001011: bYc <= cpuDO; //Y start copy
6'b001100: bXp <= cpuDO; //X start paste
6'b001101: bYp <= cpuDO; //Y start paste
6'b001110: Xp <= cpuDO; //X for pixel plot
6'b001111: Yp <= cpuDO; //Y for pixel plot
//6'b010000 reserved for hoffset on previous PVB's
//6'b010001 reserved for voffset on previous PVB's
6'b010010: fXlen <= cpuDO; //X length of fill
6'b010011: fYlen <= cpuDO; //Y length of fill
6'b010100: fXs <= cpuDO; //X start
6'b010101: fYs <= cpuDO; //Y start
6'b010110: htiming[VIDEO] <= cpuDO; // htiming[VIDEO] = 1920;
6'b010111: htiming[FRONT] <= cpuDO; // htiming[FRONT] = 160;
6'b011000: htiming[SYNC] <= cpuDO; // htiming[SYNC] = 438;
6'b011001: htiming[BACK] <= cpuDO; // htiming[BACK] = 120;
6'b011010: vtiming[VIDEO] <= cpuDO; // vtiming[VIDEO] = 1080;
6'b011011: vtiming[FRONT] <= cpuDO; // vtiming[FRONT] = 44;
6'b011100: vtiming[SYNC] <= cpuDO; // vtiming[SYNC] = 85;
6'b011101: vtiming[BACK] <= cpuDO; // vtiming[BACK] = 2;
6'b011110: cX <= cpuDO; //X for character plot
6'b011111: cY <= cpuDO; //Y for character plot
6'b100000: cC <= cpuDO; //background pixel color
6'b100001: Charsize <= cpuDO;
6'b100010: Att <= cpuDO; //Attributes [15:8], 8-bit character value [7:0]
endcase
I tried the idea, but it got hairy real quick. After about 2hrs of writing the Verilog code, simulations revealed that the way I had envisioned this was not going to work due to timing issues and it was not worth the time investment that I was beginning to realize. To compound this issue, I forgot to save the initial project success before the heavy modification. It took 4 days to get back to the last pic with the ellipse. 3 of which due to to 1 character mis-type in address decoding. I found that error this morning after extensive sim's. Stupid mistake, but finding the needle (in the haystack) gives one confidence. So I post...
. It's actually cake. The Y index values are cosines in the 'sinwave' routines. The X index values are sines. So by plotting sine/cosine in an X/Y system, you get a circle or ellipse depending on the X/Y index registers. The W index is the length of the LUT.