Should be good. At 10 ns I'd have some reservations about an intermediate connector and relatively long tracking, though.

Parts are on both sides, and the bypass capacitors are embedded in the PCB near the connector and directly under the die of each IC. Being able to stand modules up close together keeps the total length of any given net shorter than it would be if you put them all on the mother board. The layout is really just about the best it could be for the ICs' pinout and size. I'm confident that the modules will perform at least as good as you could get the same ICs to work on your mother board, if not better. I have quite a bit of experience designing mixed-signal PCBs with audio/digital/SMPSs/RF, very successful at avoiding crosstalk and keeping good behavior of all parts of the circuits. In the last one, I had a 2.4GHz antenna transmitting about 1/4" away from an embedded processor and switching power supply, and 1/2" away from analog parts. It worked very well, exceeding the boss's dreams.

We may know in the not-too-distant future if your DIMM can run at with a 65C816 at full speed. I've decided to switch gears and get cracking on building POC V2. To paraphrase a Depression Era slogan as folks migrated to California, "Twenty megahertz or bust!"

See my avatar picture for a design of mine that runs the 65C816 at 14.7 MHz on 55 ns SRAM. It sure is borderline. After all, at 14.7 MHz, a half-cycle is only 34 ns, so anything based on phi2 is not enough time. Thankfully, SRAMs start their address decoding spontaneously, outside the strobe, so it actually has most of the full cycle.

See my avatar picture for a design of mine that runs the 65C816 at 14.7 MHz on 55 ns SRAM. It sure is borderline. After all, at 14.7 MHz, a half-cycle is only 34 ns, so anything based on phi2 is not enough time. Thankfully, SRAMs start their address decoding spontaneously, outside the strobe, so it actually has most of the full cycle.

According to the '816 data sheet timing specifications, there's only 30ns guaranteed for tACC on a 14MHz '816. tADS can be as high as 30ns and tBAS can be as high as 33ns, eating up nearly the entire phase-1 time.

On the topic (or should I say off-topic ) of '816 timing, I agree the WDC timing spec is conservative. Also not terribly easy to comprehend!

Allow me to re-post (from this thread) my own edited version of Figure 4-1 from the '816 Data Sheet (Sept 2010 version). To put all the various delays in perspective I squeezed and stretched things so that the diagram is now approximately to scale along the horizontal axis. 5V operation is assumed.

-- Jeff
[Edit: fix image so it will enlarge]

I saw this a few days ago while I was doing a timing analysis on the decoding scheme that I'm planning on trying, and was shocked. With tPWL at 35ns and tADS at 30ns you have 5ns to set the chip selects on your 6522 before phi2 heads north for the summer. If you also want to involve the bank address, tBAS at 33ns means you have 2ns left to set those chip selects. Or, at least, to trigger a wait-state or something. I guess the other angle is to delay the phi2 signal going to the VIA, I haven't looked into how that works out for read/write timing.

According to the '816 data sheet timing specifications, there's only 30ns guaranteed for tACC on a 14MHz '816. tADS can be as high as 30ns and tBAS can be as high as 33ns, eating up nearly the entire phase-1 time. The read data setup time tDSR (the amount of time data has to be ready before the fall of phase 2) is specified to be 10ns max. Glue logic further eats into the time budget. Fortunately, actual parts are usually much faster than the specifications say, and you're probably also not running things at the upper temperature extreme where they're the slowest. Otherwise, 55ns SRAM would not stand a chance of running on an '816 at 14.7MHz, according to the specs.

The question isn't whether the SRAM can do it. It's whether the bus loading caused by the DIMM will sabotage the quest for full throttle.

You should not put too much faith in timing information in datasheets. If timing is tight, you should measure.