Hello, I need to delay a 1-bit signal by 6 cycles. What is a more proper/cleaner way to do the following? I know a multistage shift register would work, but not sure how to code it.

TIA

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Your method works, and if you're lucky the tools will synthesize a shift register. But you can also make an explicit shift register yourself:

I checked the RTL schematic. My code shows multiple FF's in a row which was expected. Your code works, but I cannot see it in the RTL schematic.

I'm puzzled about your code, I would have expected a '<<' or '>>' somewhere. How does the Verilog know that this is a shift register?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The { } is the concatenation operator. It combines multiple bits. In this case it takes s[4:0] as the most significant bits, and add countflag as the least significant bit. If you write s <= { countflag, s[5:1] } it's a shift register to the right.

Ah... Thanks! I was thinking 'replaces' which would result in no action.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Replacing the least significant bit would look like { s[5:1], countflag }

Excellent! Why then isn't your code showing up in the RTL schematic? Has it been absorbed? Is this the ideal situation when using Verilog?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I don't know. Are you using the input and output ? If not, it may have been optimized away. I just tried it in ISE, and it shows up in the RTL schematic as 6 FFs. In the technology schematic is shows up as a single slrc16e.

Arlet, in your example I imagine you wanted to use q and not countflag... You can make it even simpler without a temporary:
and possibly even simpler:

Verilog should trim the high bit when assigning the 7-bit result to a 6-bit register. I think. I am away from my system to check. Maybe it's an error condition, but verilog is generally pretty permissive.

Of course in the real world to get any data into s you'll have to mux it in somewhere.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

No, countflag is the input, and q is the 6-cycle delayed output.

oh, I see, it's just a streaming shift register. My mistake, I was rotating for some reason.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I can't remember for sure, but I think verilog allows aggregate lvalues:

Am I wrong?

[Edited typos]

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

OK, here is my favorite way to do this:

This little gem creates a shift register inside a single LUT. 1,0,1,0 is backwards binary 0101 - decimal 5, which creates a tap at the 6th bit.

This method is a little frowned upon since it binds you to Xilinx chips. Personally I am sold, so I write a lot of code like this (I prefer instantiation as it more closely resembles a netlist or a schematic. As I see it, it's more readable for some types of circuits).

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

My code also creates a shift register inside a single LUT, so it comes down to what you find easier to express.

To be totally accurate, instantiating guarantees that an SRL16 will be created. Otherwise, it is merely likely that a single SRL16 will be created and not a bunch of flip-flops. It depends on the settings buried in command-line switches and project settings.

An instantiated SRL16 may also be manually placed at a specific location on the chip.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut