W65C134S: Design Questions, Please?

[Michael]

Hi guys,

I just stumbled across a pair of W65C134S samples that I received way back in 1997 and I'd like to try and design a simple SBC with one of them. My goal is to design a small but capable SBC with 32kB RAM and a 128kB emulated disk on serial eeprom. Since I've never built a SBC before and I haven't found any example W65C134S SBC projects for reference, could I impose on you kind folks for guidance, please?

The W65C134S is an interesting beast. It has a built-in Monitor ROM and a handful of built-in peripherals, including an ACIA. Now, if I'm interpreting the documentation correctly, I should be able to bring it "up" in a minumum configuration with just a 32768 Hz crystal for 'CLK', a 2.0 or 4.0 MHz crystal for 'FCLK' (fast clock), a 'reset' circuit, a few passive components, and a usb-to-serial (ttl level) adapter. Mind you, this minimum configuration will only have 192 bytes of built-in RAM which is mirrored between the ZP and Stack at $0040..00FF and $0140..01FF, but I can do just about anything I want with the RAM using Monitor commands via a terminal program on my PC.

Question 1: Can I use a PIC to generate FCLK?

I've got a 32768 Hz watch crystal but I don't have a crystal in the correct range for FCLK. The WDC evaluation boards use "can" crystals so I'm thinking I should be able to use a TTL level clock signal from a PIC, yes, no? I know you're thinking I should just spring for a crystal but I'd rather use what I have at hand, and besides, I'm hoping I can use the little 8 pin PIC for another function on the SBC (read on).

Question 2: Generating a PHI2 qualified /WE signal for RAM

After I get the board up-n'-running in the "minimum configuration" mentioned above, I'd like to add a 32Kx8 SRAM. I think that will involve setting a register bit in the W65C134S to turn on the built-in chip select output for the RAM chip, and if I'm not mistaken, I need to develop a /RD signal and a PHI2 qualified /WR signal for my RAM chip just like BDD does in his POC board design. Is this correct? If so, can I use the CLC (Configurable Logic Cell) in my PIC?

As far as I know, Microchip hasn't published any specs for the CLC modules so I don't know what kind of propagation delay I'd have. However, if the CLC is fast enough, I would have the read/write logic and the FCLK source all on a little 8 pin PIC, which would be kinda' cool.

TIA, guys... Cheerful regards, Mike

CLC #1.png (11.74 KiB) Viewed 1124 times

[GARTHWILSON]

Michael wrote:

Question 1: Can I use a PIC to generate FCLK?

I've got a 32768 Hz watch crystal but I don't have a crystal in the correct range for FCLK. The WDC evaluation boards use "can" crystals so I'm thinking I should be able to use a TTL level clock signal from a PIC, yes, no? I know you're thinking I should just spring for a crystal but I'd rather use what I have at hand, and besides, I'm hoping I can use the little 8 pin PIC for another function on the SBC (read on).

It looks like you can tell the PIC how fast you want its internal clock to run, and then you can use CLKOUT to output 1/4 of that frequency. In my 10 minutes looking at the data sheet, I did not see what the resolution is on the speed you set it to run at, if you can run it at 16MHz so it outputs 4MHz. Note however that its frequency may not be exact enough to run RS-232 on (if it gets used for that), unless you also give the PIC a crystal reference. They say you can get it to 1% which may work, but I don't know yet if it can hold 1% across the temperature range.

Quote:

Question 2: Generating a PHI2 qualified /WE signal for RAM

After I get the board up-n'-running in the "minimum configuration" mentioned above, I'd like to add a 32Kx8 SRAM. I think that will involve setting a register bit in the W65C134S to turn on the built-in chip select output for the RAM chip, and if I'm not mistaken, I need to develop a /RD signal and a PHI2 qualified /WR signal for my RAM chip just like BDD does in his POC board design. Is this correct? If so, can I use the CLC (Configurable Logic Cell) in my PIC?

As far as I know, Microchip hasn't published any specs for the CLC modules so I don't know what kind of propagation delay I'd have. However, if the CLC is fast enough, I would have the read/write logic and the FCLK source all on a little 8 pin PIC, which would be kinda' cool.

Yes, that CLC that allows you to set up logic functions without their having to go through instructions is really neat! So is the numerically controlled oscillator. I didn't see any propagation-delay specs either.

About the EEPROM: I've used the 24-family serial I²C ones, and I like them, but you can get much higher density and higher speed with SPI ones. Right now I'm working with the 25VF032 which is 4Mx8 in an SO-8 package.

[Michael]

GARTHWILSON wrote:

Michael wrote:

Question 1: Can I use a PIC to generate FCLK?

I've got a 32768 Hz watch crystal but I don't have a crystal in the correct range for FCLK. The WDC evaluation boards use "can" crystals so I'm thinking I should be able to use a TTL level clock signal from a PIC, yes, no? I know you're thinking I should just spring for a crystal but I'd rather use what I have at hand, and besides, I'm hoping I can use the little 8 pin PIC for another function on the SBC (read on).

It looks like you can tell the PIC how fast you want its internal clock to run, and then you can use CLKOUT to output 1/4 of that frequency. In my 10 minutes looking at the data sheet, I did not see what the resolution is on the speed you set it to run at, if you can run it at 16MHz so it outputs 4MHz. Note however that its frequency may not be exact enough to run RS-232 on (if it gets used for that), unless you also give the PIC a crystal reference. They say you can get it to 1% which may work, but I don't know yet if it can hold 1% across the temperature range.

I can run the PIC at 8 or 16 MHz to get a 2 or 4 MHz output for the W65C134S "fast clock".

You're right, of course. I may have to use a crystal.

Quote:

Quote:

Question 2: Generating a PHI2 qualified /WE signal for RAM

After I get the board up-n'-running in the "minimum configuration" mentioned above, I'd like to add a 32Kx8 SRAM. I think that will involve setting a register bit in the W65C134S to turn on the built-in chip select output for the RAM chip, and if I'm not mistaken, I need to develop a /RD signal and a PHI2 qualified /WR signal for my RAM chip just like BDD does in his POC board design. Is this correct? If so, can I use the CLC (Configurable Logic Cell) in my PIC?

As far as I know, Microchip hasn't published any specs for the CLC modules so I don't know what kind of propagation delay I'd have. However, if the CLC is fast enough, I would have the read/write logic and the FCLK source all on a little 8 pin PIC, which would be kinda' cool.

Yes, that CLC that allows you to set up logic functions without their having to go through instructions is really neat! So is the numerically controlled oscillator. I didn't see any propagation-delay specs either.

If I had a scope I would be happy to do some experiments to characterize CLC performance. In the mean time, I'll just try it and see if it works.

Quote:

About the EEPROM: I've used the 24-family serial I²C ones, and I like them, but you can get much higher density and higher speed with SPI ones. Right now I'm working with the 25VF032 which is 4Mx8 in an SO-8 package.

I've seen those and they're pretty cool but I'd like to stay with 5v DIP units for now which pretty much limits me to the lower density units.

Take care... Have fun... Regards, Mike

<added>

I'm starting to wire up a W65C134S test board...

6502.org wrote:

Image no longer available: http://forum.allaboutcircuits.com/attachment.php?attachmentid=52393&d=1361506174

[GARTHWILSON]

Michael wrote:

GARTHWILSON wrote:

About the EEPROM: I've used the 24-family serial I²C ones, and I like them, but you can get much higher density and higher speed with SPI ones. Right now I'm working with the 25VF032 which is 4Mx8 in an SO-8 package.

I've seen those and they're pretty cool but I'd like to stay with 5v DIP units for now which pretty much limits me to the lower density units.

You can use the SOIC-to-DIP adapters like this one from Jameco:



That's what I'm using with the 25VF032. I'm also using it on a 5V system, with an LM339 for logic-level conversion as shown at http://wilsonminesco.com/6502primer/pot ... HI_V_LOGIC . You could also use the 74LS07 or the 74LVXxx family for logic-level conversion. If you want purely 5V though, I was going to suggest the AT45D161 2Mx8 which I have a couple of here that I'll never use, but it looks like it's no longer made. There's the 45DB161 (and denser brothers), but it's 3.3V.

I can't remember if I mentioned this before, but for an I²C port, let me recommend our I2C-6 pinout. Daryl has EEPROM modules available in this pinout, and uses the same pinout on his SBC-4 computer.

[Michael]

Thanks for the info', Garth. I saw the thread with the I2C specification you mentioned. Very nice!

New question, if I may?

While reading the W65C134S Monitor ROM Reference Manual, Release 2.0 (February 7, 1995), I noticed that the serial routines use hardware hand shaking. Does anyone know if I can bypass the input signal from the PC host by tying the NE47 line (pin 61) on the W65C134S to ground?

TIA, Gentlemen. Cheerful regards, Mike

[GARTHWILSON]

Quote:

While reading the W65C134S Monitor ROM Reference Manual, Release 2.0 (February 7, 1995), I noticed that the serial routines use hardware hand shaking. Does anyone know if I can bypass the input signal from the PC host by tying the NE47 line (pin 61) on the W65C134S to ground?

If NE47 is truly set up for negative-edge interrupt, I think you would want to pull it up to Vcc through a resistor. I don't find anything in either the data sheet or the ROM reference manual about NE47 being used by the serial routines though. What did you find? How is it used?

[Michael]

Well, I have the older 1995 ROM Reference Manual but the same info' is on page 15 in the new ROM Reference Manual on the WDC web site;

[GARTHWILSON]

So it looks like a CTS input. If you make it look like the other end can always accept data, the '134 might send data that will be lost because the other end is in fact not ready. It seems like that should never happen if the other end is a multi-GHz PC, but I've seen such PCs ignore the keyboard for several seconds, a problem our son never had on a 1MHz Commodore 64 with GEOS when writing papers in junior high, so I don't know.

[Michael]

I was hoping I could just tie that pin low and not worry about it. I haven't looked at the Monitor ROM listing yet. Perhaps the Monitor is just testing that pin for a low level rather than a negative going edge?

Thank you, Sir... Back to wiring up the board...

Cheerful regards...

[rwiker]

Michael wrote:

I was hoping I could just tie that pin low and not worry about it. I haven't looked at the Monitor ROM listing yet. Perhaps the Monitor is just testing that pin for a low level rather than a negative going edge?

There's a long tradition for hardwiring handshaking signals, so I doubt that these are edge-sensitive. That said, handling these correctly only requires some extra level shifters (and maybe not even that, as there is (I think) cables available that interfaces USB to 3.3V serial... some FTDI thing, I guess.)

Of course, if you actually have real RS232 ports, you'll need real drivers, too

[Michael]

No, I'm not using "real" RS232 ports. Instead I usually use a small USB-to-Serial (TTL level) board with PL2303 or CP2102 chipset (less than $3 on ebay, including shipping) or a Chinese clone of the Nokia CA-42 USB-to-Serial (TTL level) cable (also less than $3 on ebay, including shipping). I replace the cell phone connector on the CA-42 cable with a 3.5mm stereo plug. Both adapters allow me to add USB serial connectivity to any project by simply adding a 3 or 4 pin header or a 3.5mm stereo jack to my project boards.

You can just see one of those adapters plugged into my laptop near the top of this picture which is being used to power and connect a PIC prototype board in the foreground with my laptop.

Regards, Mike