Hi guys,
I just stumbled across a pair of W65C134S samples that I received way back in 1997 and I'd like to try and design a simple SBC with one of them. My goal is to design a small but capable SBC with 32kB RAM and a 128kB emulated disk on serial eeprom. Since I've never built a SBC before and I haven't found any example W65C134S SBC projects for reference, could I impose on you kind folks for guidance, please?
The W65C134S is an interesting beast. It has a built-in Monitor ROM and a handful of built-in peripherals, including an ACIA. Now, if I'm interpreting the documentation correctly, I should be able to bring it "up" in a minumum configuration with just a 32768 Hz crystal for 'CLK', a 2.0 or 4.0 MHz crystal for 'FCLK' (fast clock), a 'reset' circuit, a few passive components, and a usb-to-serial (ttl level) adapter. Mind you, this minimum configuration will only have 192 bytes of built-in RAM which is mirrored between the ZP and Stack at $0040..00FF and $0140..01FF, but I can do just about anything I want with the RAM using Monitor commands via a terminal program on my PC.
Question 1: Can I use a PIC to generate FCLK?I've got a 32768 Hz watch crystal but I don't have a crystal in the correct range for FCLK. The WDC evaluation boards use "can" crystals so I'm thinking I should be able to use a TTL level clock signal from a PIC, yes, no? I know you're thinking I should just spring for a crystal but I'd rather use what I have at hand, and besides, I'm hoping I can use the little 8 pin PIC for another function on the SBC (read on).
Question 2: Generating a PHI2 qualified /WE signal for RAMAfter I get the board up-n'-running in the "minimum configuration" mentioned above, I'd like to add a 32Kx8 SRAM. I think that will involve setting a register bit in the W65C134S to turn on the built-in chip select output for the RAM chip, and if I'm not mistaken, I need to develop a /RD signal and a PHI2 qualified /WR signal for my RAM chip just like BDD does in his POC board design. Is this correct? If so, can I use the CLC (Configurable Logic Cell) in my PIC?
As far as I know, Microchip hasn't published any specs for the CLC modules so I don't know what kind of propagation delay I'd have. However, if the CLC is fast enough, I would have the read/write logic and the FCLK source all on a little 8 pin PIC, which would be kinda' cool.
TIA, guys... Cheerful regards, Mike
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