GARTHWILSON wrote:
What you do is to have the PCB design in CAD in front of you, in a copy that you can destroy as you go. It's best to have two people on this (one on a paper copy of the schematic and one on the CAD), but I normally don't have any help. You pick a net on the schematic, follow it on the CAD, marking the schematic with a colored pencil as you check that net on the CAD, then when you're satisfied that the net goes to everying thing it should on the layout and not to anything it should not go to, delete that net on the CAD. Now it's deleted on the CAD and marked on the paper schematic. If you find an error, write it down, or fix it in another window. As parts get all the nets they're connected to checked and deleted, delete the part also. If there are errors, they will show up. You might find for example that you're left with a line on the schematic that's not marked and there's nothing left on the board, because that line did not get routed.
That's the method I've used for a long time to weed out layout errors. It's quite effective and I recommend it to anyone trying to lay out a PCB. It sure beats throwing away PCBs that are discoverd to have an intractable error after they have been made and paid for.
Quote:
Going beyond two-layer is where the cost starts going up more because they have to make multiple thinner boards and then laminate them together.
The cost differential is coming down and square inch for square inch, a four-layer board is about 60 percent the size of an equivalent two-layer design. The advantages go well beyond physical size. Four-layer designs, in which the inner layers handle power and ground, are potentially a lot less noisy, generally allow increased component density (you're not having to use up space for power and ground runs) and greatly reduce voltage fluctuations and ground bounce, the latter which sabotages a lot of designs. I did my POC unit on a four-layer board and it proved to be stable at 12.5 MHz (maximum speed the I/O hardware would tolerate). In fact, in a fairly recent test, I removed all the decoupling capacitors and it still was stable at 12.5 MHz. That would be attributable to the fact that the inner power and ground layers act as a giant bypass capacitor and were able to sink most of the switching noise. However, don't take this to mean you should forego decoupling caps. Any good design will have one for each active device on the board.
Login
Register
FAQ
Search
