Mike Chambers wrote:
but when phase 2 goes low, the correct data is still on the bus isn't it? i'm am using both phase 2 and the condition of the correct address of the 373 latch being on the lines, through an AND gate to qualify the latch to grab whats on the bus.
i have yet to see any incorrect data get sent out to the parallel port.
The problem is not when phi2 goes low, it is when phi2 goes high. The data bus is NOT valid at this time. The '373 reads incorrect data from the bus, outputs it. Then before phi2 gets low again, the cpu outputs correct data, the '373 fetches it and displays it of course. So with a static measurement (after the cycle) you will never see the wrong data.
But look at it with a 'scope, you will see the glitches.
You could check that with a simple flip-flop: take a '74, connect its /Q to D so it toggles its state on every clock transition (IIRC low-high). Then connect its clock input to a '373 output. Now repeatedly write the same(!) value to the '373. You would expect that the '74 output will not change. However, you will notice that some times the '74 output changes. This is because the it gets a glitch from when phi2 goes high until the cpu puts the correct data on the bus.
These glitches are horribly hard to find and I would try to avoid them at all cost actually.
Of course, if all you do is light some LEDs, and not try to control something else, you should be ok.
André
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