problem using 74LS373N data latch to verify bit pattern

[Mike Chambers]

hi, i'm new to designing/building computers but i'm creating a 6502-based computer on a breadboard. i've got it successfully running code, verified by single-stepping with the LEDs on the EEPROM data output and the values match up.

my problem is, i've now added a 74LS373N octal latch which i am attempting to map so that it latches the data writes to any address under $8000. i've got code on the EEPROM that does an endless loop of:

LDA #$AA
STA $0000

so that it is always writing 10101010. i have the data bus wired to the latch, and 8 LEDs on it's output but all it seems to do is light up the patterns based on what being read from the ROM.

i must not be wiring this up right. can anybody help me out with how the LS373 should be connected to pull this off?

should i be inverting both the 6502 R/W and A15 lines, ANDing the two inversions together, invert the output of that AND, and send that inversion to the CLK pin on the LS373?

thanks!

[GARTHWILSON]

Can you post the circuit?

[Mike Chambers]

that was fast! i don't actually have a circuit schematic made up, i've just been sitting over the breadboard with data sheets and experimenting. give me a little bit and i'll post a schematic. thanks.

[Mike Chambers]

what's a good program for designing a schematic? i've never done it on a computer, and i'm not that great with them in general. i don't have a lot of design experience.

[GARTHWILSON]

I got very proficient at OrCAD at my last place of work, and I've evaluated a bunch of others, and I don't like the way any of them work for schematics (I don't have time right now to tell why), so I've been doing schematics by hand in recent years. Just sketch it and scan it and post a .jpg. (Obviously I've been using CAD to lay out PC boards.)

[Dajgoro]

Try: NOT(A15) AND Ф2 AND NOT(R/W)
I am not sure if it will work, if i got it right it should.
When using devices that don't support this kind of synchronous bus, you must always sync the enable pin with clock phase 2 of the cpu.
I've added some latches to my sbc(they do work), and if it won't work again, i could take a look how i wired it up there(i don't have the schematic).

[Dr Jefyll]

Mike Chambers wrote:

should i be inverting both the 6502 R/W and A15 lines, ANDing the two inversions together, invert the output of that AND, and send that [...] to the CLK pin on the LS373?

The Latch Enable input (sometimes misleadingly referred to as CLK) on the '373 is active high. That is, being at a high level allows new data to be entered. Instead, the circuit you describe produces a low at the time you want new data to be entered. (I think I understand your description. But a diagram is more precise -- hence Garth's request.) You need to omit the part that I've underlined.

Also, as Dajgoro points out, we need to include Ф2. That's in order to more exactly determine the time new data is to be entered. There's often garbage (invalid data) on the bus as it changes states in the transition between one cycle and the next. Including Ф2 guarantees we're operating strictly during the stable part of the cycle, as desired. So your recipe is

Quote:

inverting both the 6502 R/W and A15 lines, ANDing the two inversions together, also ANDing with Ф2, and send that (the AND output) to the CLK pin on the LS373

cheers,

Jeff

[BigEd]

Mike Chambers wrote:

what's a good program for designing a schematic? i've never done it on a computer, and i'm not that great with them in general. i don't have a lot of design experience.

For a small logic design problem, you might want to have a look at Logic Friday "Free software for boolean logic optimization, analysis, and synthesis" (for Windows, works in WINE for Linux too)

(via a discussion on stardot)

Cheers
Ed

[Mike Chambers]

Dajgoro wrote:

Try: NOT(A15) AND Ф2 AND NOT(R/W)
I am not sure if it will work, if i got it right it should.
When using devices that don't support this kind of synchronous bus, you must always sync the enable pin with clock phase 2 of the cpu.
I've added some latches to my sbc(they do work), and if it won't work again, i could take a look how i wired it up there(i don't have the schematic).

Dr Jefyll wrote:

Mike Chambers wrote:

should i be inverting both the 6502 R/W and A15 lines, ANDing the two inversions together, invert the output of that AND, and send that [...] to the CLK pin on the LS373?

The Latch Enable input (sometimes misleadingly referred to as CLK) on the '373 is active high. That is, being at a high level allows new data to be entered. Instead, the circuit you describe produces a low at the time you want new data to be entered. (I think I understand your description. But a diagram is more precise -- hence Garth's request.) You need to omit the part that I've underlined.

Also, as Dajgoro points out, we need to include Ф2. That's in order to more exactly determine the time new data is to be entered. There's often garbage (invalid data) on the bus as it changes states in the transition between one cycle and the next. Including Ф2 guarantees we're operating strictly during the stable part of the cycle, as desired. So your recipe is

Quote:

inverting both the 6502 R/W and A15 lines, ANDing the two inversions together, also ANDing with Ф2, and send that (the AND output) to the CLK pin on the LS373

cheers,

Jeff

beautiful, that did it! thanks for the input, everybody. the LEDs now show $AA. that was awesome, i think i need to put on some fresh pants.

i got rid of a little of the complexity as well for being able to add RAM and I/O space now by sticking a 74LS139 into the mix. i forgot to pick one up the other night when i stopped by the local electronics parts store, so i had to resort to desoldering one from a long-dead 8088 motherboard.

i'm also using it's 8284A so i didn't have to make my own clock circuit. so now i can get to adding SRAM and a parallel I/O interface. i'm a bit excited, i've always wanted to build a little computer like this. i tried in the past with an 8088, but it got a bit tricky and i gave up.

[Nightmaretony]

My fave schematic and pcb draw, Kicad.

[Mike Chambers]

kicad looks excellent! i think i will make up some schematics for this now before it gets too much more complicated, so i can share the design when it's done. i've got it running code i wrote and stuck on a ROM that so far just splits a big string into high/low nibbles, and sends them out through a parallel interface to an old 486 laptop:

http://www.youtube.com/watch?v=0QLxcND-7uM


i just have to add some RAM, and also have it support input via parallel from the laptop. at that point, all it would need is some good code to make it useful.

[ElEctric_EyE]

Interesting you got a '373 working as an output port. I used to use '373s as input latches and '374s as output FF's.
Anyway, glad you got it working. Electronics is awesome when it works, isn't it!

Good Luck!

[Nightmaretony]

Mike, the best part I love about Kicad is being free and open source. Already had some good layouts in using it so I am hooked. Was certified in Pads previously and had some experience with Pcad. Am lovin Kicad the most.

[fachat]

Without looking at the schematics, I would not recommend using a '373 as output latch. This almost guarantees glitches on the output signals.

When the '373 is enabled, the signals are "transparent" according to my data book. So if they are enabled when phi2 goes high, but the CPU has not (yet) put the data on the data bus, the chip will happily read anything from the databus and send it out. Only when the CPU has come around to putting the correct data on the bus shortly before phi2 goes low again the output will be correct.

André

[Mike Chambers]

fachat wrote:

Without looking at the schematics, I would not recommend using a '373 as output latch. This almost guarantees glitches on the output signals.

When the '373 is enabled, the signals are "transparent" according to my data book. So if they are enabled when phi2 goes high, but the CPU has not (yet) put the data on the data bus, the chip will happily read anything from the databus and send it out. Only when the CPU has come around to putting the correct data on the bus shortly before phi2 goes low again the output will be correct.

André

but when phase 2 goes low, the correct data is still on the bus isn't it? i'm am using both phase 2 and the condition of the correct address of the 373 latch being on the lines, through an AND gate to qualify the latch to grab whats on the bus.

i have yet to see any incorrect data get sent out to the parallel port.