Unfortunately, the spacing of the rows in a 64pin DIL is too tight to fit a 144 TQFP between them. Unless you decapitate a few pins as John Kortink did in his ReTuLa product.

Here's a sketch:

As you see, this offers a 64 pin DIL, a 128-pin shielded option with 64 I/Os, and a 40-pin DIL option(*). I don't know if it's routable. (It's a pity the RAM pins are too tight to allow routing between them.)

I wonder if this 64/128 pin approach will be better mechanically than the 120-pin square approach, which might be nearly impossible to unplug?

I have to say, I don't believe in the absolute need for these super-short RAM busses. Example: XO-1 runs a 4-chip SDRAM bus at 166MHz. An inch or two shouldn't be an issue. Maybe EEye's experience will tell us something, when he gets to that stage.

Cheers
Ed

(*) For the 40-pin DIL I'd ideally like to add level converters... they come in 6.2mm or 4.4mm width packages. Placeable, but I'm not sure about routeable. See page 16 of the GODIL user guide for some usage details.

You mean something like this?

yes! That should be about the same as my sketch in the previous post.

As to how we'd order the I/Os, that's up for grabs. Generally one would want to make it easy to interface with a memory bus. As the point here is large memory, we should probably look to the signal order on DIMM or SODIMM, as well as the order on SDRAM components.

Fortunately re-ordering signals is very easy on FPGA.

Cheers
Ed

Would it be ok for a side hanging of the sub board off the 40 pin socket?

http://www.system16.com/hardware.php?id=773

bottom right on this sub-board, note the daughterboard with the overhang...

_________________
"My biggest dream in life? Building black plywood Habitrails"

I expect we will do that, because the decapitation approach isn't likely to appeal.

So we end up with something like my earlier 40-pin sketch, but scaled up to 64-pin (plus optional shields, plus an embedded 40-pin.)

Instead of a standard DIL-64, why not increase the spacing a little bit, so the FPGA fits inbetween ? It won't fit a standard IC socket, but you can use some header strips instead.

It won't be a drop-in replacement for a 64 pin IC anyway, so there's not much advantage to using a standard socket.

As already noted I think, the square (rather than DIL) layout keeps traces short and consumes less board real estate. Here's a 104-pin layout. Compared to a 64-pin DIL there may be a slight mechanical issue -- it may be harder to unplug -- but that's manageable in various ways.

Re the provision of extra pins for ground plane: Rather than allowing 100% extra -- ie, one ground pin per signal pin -- I propose a smaller (but still generous) proportion. For example, 50% extra would allow two-thirds of the pins to be signal pins -- and yet every signal pin would still be adjacent to a ground pin.

BTW it seems to me that, to further reduce pin count, some of the "ground" pins could actually be the pins that carry supply voltages between the motherboard and daughterboard. Is this reasonable? In terms of reflections and other AC effects, the supply pins are ground (presuming they connect to nearby bypass cap's both on the motherboard and daughterboard).

-- Jeff

That's what I did on my 4Mx8 5V 10ns SRAM module which is available now. (Data sheet here.) The pinout has:

where each "s" is a signal line and each "X" is a ground or bypassed power which for AC purposes is virtual ground; so no signal pin is more than .2" away from a ground or virtual ground.

http://WilsonMinesCo.com/

Yes, exactly. Sorry for presenting redundant material.



Here are a couple of alternative layouts, using a ratio of 3:1 and 3.5:1 signal pins per ground/power pin. (Of course even larger ratios would work.) Since the power and ground pins ( + and - ) are always adjacent, surface-mount bypass caps could be located within the header footprint (ie, between the pins).

-- Jeff

The ground plane will go around all the pins anyway, so if the Vcc pins are bypassed to the ground plane around them, there's no need to have them adjacent to, and paired with, the ground pins. This reduces the requirement for so many pins just to get all the signal pins suitably close to ground or virtual-ground pins.

Having chip capacitors between pins on a header would be nice, but with .040" holes (to accommodate .025" square pins), an 0603 capacitor is probably too big. 0402 is getting awfully hard to install by hand; and then you have to consider that the chip capacitors really need to be put on before the header goes on, and then getting the header on might be an extra challenge. I think I'd have to try it before I could say it was do-able. The chip capacitors might have to go outside the two rows of pins.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

On the daughterboard, yes. But it would be nice to have caps on both ends of the mating headers (male & female). The motherboard might not have a ground plane, so the option of caps between the pins may yet prove modestly helpful.

Darn dicey soldering, though, as you say.

Even if the motherboard is wire-wrapped (if WW will work at all at these speeds), it should be done on perfboard with plated-thru holes and a plane on at least one side, like this one from Twin Industries:
Edit, leaving the old URL to rattle their cage:

This lets you solder a chip capacitor from a pin to the surrounding ground plane. This board is less than $20US for 4.5"x6.5", and less than $12US for 4"x6". 4"x10" is priced at $23.60. They also have ones with planes on both sides for the same prices, which is way cheaper than Vector used to have them.

If the mother board doesn't have a ground plane, I don't think cap.s between the pins will do much good.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Super-short is not absolutely necessary, but if they're not so short, you have to closely control the characteristic impedance of the transmission lines, terminate them properly, etc.. It's done all the time in commercial designs by engineers who are very familiar with this stuff and have an inventory of test equipment available to them that's worth more than my house; but for us hobbyists and midnight engineers, it's better to stay out of that territory by keeping connections really short and observing "good engineering practice." (Don't you just love that nebulous engineering term we use when we don't have what it takes to accurately model a circuit.)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

To summarise where we are with this:
- not a lot of expressed interest, so even a run of 6 boards is a bit of a risk
- which makes in tempting to include everyone's wishlist

So perhaps just the preprogrammed non-volatile FPGA for a few dollars makes more sense, and let people get on with their own board design.

That is, presume that it's the FPGA/verilog which is the stumbling block, not the surface mount (or the 3V interface).

I'd be interested to hear more details from the voter who wanted 'something else'.

Cheers
Ed