65Org16 CPU module / general FPGA breakout board idea

[Dr Jefyll]

GARTHWILSON wrote:

put the RAM IC on the opposite side of the same board

I agree that's the most ideal solution. And your technique to put caps inside the board would come in handy here! But I'm not the one doing the work, and it'd probably be easier to design two simple boards (each freely using copper and caps on the backside) than a single, more complex board.

The cost difference may be minimal, depending whether the single-board approach demands 4-layer construction.

In any case I think we want to steer away from putting the FPGA and RAM side by side on the same board. Many of the interconnects end up looping around the devices, whereas the 3D approach keeps all interconnects fairly short.

-- Jeff

[GARTHWILSON]

Quote:

The cost difference may be minimal, depending whether the single-board approach demands 4-layer construction.

For such fast parts I think I would want to do 4-layer anyway, to reduce the distance between signal traces and the ground under them, to reduce coupling between traces that are close together. Going to a thinner board helps somewhat, but I don't know how thin it can safely go without danger of breaking if there's no method especially to eject the pins evenly from the sockets. Maybe there ought to be some kind of plan anyway, even just to avoid bending the pins. If someone has an idea of how to do that, or links to articles on how thin boards can safely go for this kind of thing, I'm all ears.

[ElEctric_EyE]

Maybe someone can start a poll on whether or not to include more IC's on the breakout board, thereby raising cost...

Even before then, we need to establish the FPGA internal block RAM usage. Even before that, we need agree on an FPGA...

But, as far as internal Block RAM usage I would suggest a memory map like the following. It jives with Bitwise' 65Org16 assembler that converts original NMOS6502 to 65Org16:

$00000000-$000000FF Zero-Page (for original NMOS6502)
$00000100-$0000FFFF Zero-Page extended (for 65Org16)
$00010000-$0001FEFF Stack extended (for 65Org16)
$0001FF00-$0001FFFF Stack (for orginal NMOS6502)

The internal block RAM memory for original stack or zero page could be extended, seeing as how they only use 512x16 block RAM. I would think this could most likely be expanded as most users would implement their ROM's using a standard external EEPROM/FLASH.
Then there's the issue of copying a user's ROM code from external ROM to internal block RAM, so the system could run incredibly faster...

Any thoughts?

[ElEctric_EyE]

Looking at the available block RAM in an XC3S50AN, only 54Kbits is available. That leaves around 3Kx16 for the 65Org16 core, and 2x that for a 6502 core. Not too much left for program space...

Maybe block RAM should be used only for stack and zero page, and the user program run from an external memory. This would at least save the user from having to use additional memory ICs for stack and zero page.

Looking at a popular 16bit wide memory device that can be programmed in say a Genius G540/Willem (I don't think there are any), the real challenge is finding an older x16 DIP style device in the 3.3V range. I don't think there are any of those either...

Sorry, didn't mean to take control of the thread, but I did have to tie that loose end up, in case anyone else was wondering...

[Arlet]

For program memory I'd use a simple serial flash, and a bootloader to copy from flash to RAM. That way you only need one parallel device. RAM access time is also lower, so it'll run faster. Programming the flash can be done from the FPGA, so you don't need a programmer. After boot, the block RAM with the bootloader can be reused as fast RAM.

[ElEctric_EyE]

Arlet wrote:

For program memory I'd use a simple serial flash, and a bootloader to copy from flash to RAM. That way you only need one parallel device. RAM access time is also lower, so it'll run faster. Programming the flash can be done from the FPGA, so you don't need a programmer. After boot, the block RAM with the bootloader can be reused as fast RAM.

Excellent suggestion. I know you've mentioned it before...

Now we know the Spartan 3AN series is not suitable (at least the version we can solder).
We need to solidify the FPGA, RAM, and serial FLASH for layout purposes.
For the FPGA, I can suggest 2 versions that do come in 100-pin QFP.

1) is the XC3S50 Spartan 3, $6-$10 from various sources. Not very dense, but should do the job nicely.
2) is the XC3S500E Startan3E, ~$30 from Avnet. It can fit alot, but may be overkill.

For top speed as BigEd has mentioned there's only one choice in 144-pin QFP, and that is the Spartan 6, -3 high speed grade ~$20 from Avnet.

If we decide that top speed is critical and decide to use the XC6SLX9, we will have ~36Kx16 of internal block RAM available. That's quite alot of space and we may not even need external SRAM?...

EDIT: In contrast, the XC3S500E has ~22Kx16 internal block RAM, and the XC3S50 has 4.5K, that pretty much eliminates the XC3S50. So there are really only 2 choices: A 100-pin QFP XC3S500E @$30 or a 144-pin QFP XC6LX9 @$20

[ElEctric_EyE]

The obvious choice is the Spartan 6 IMHO, it's cheaper and has more internal memory, although the footprint is larger.

To program the Spartan 6, one could use a 20-pin SSOP serial Xilinx PROM (XCF04S) at 4,194,304 bits, enough for 1 configuration. I am doing this in the 65Org16 Devboard. It is sufficient for storing config info for the design and ROM contents. It is abit expensive @$7ea at DigiKey.

Also, Xilinx iMPACT does have the option to program the Spartan 6 on startup from a SPI FLASH device. 8Mbit serial SPI FLASH devices are cheap @<$2ea and could store a multi-configuration. One for 65Org16 core and one for a 6502 core, jumper selectable.

The operating speed could also be externally jumper selectable from an 55MHz oscillator source. A DCM/PLL could easily provide 110MHz, 55MHz, 22.5MHz, 11.25MHz, etc (up to 6 outputs IIRC). I think if a constraints file was made for the fastest speed, all other slower speeds should work without having to reprogram the .UCF file.

[Arlet]

ElEctric_EyE wrote:

Also, Xilinx iMPACT does have the option to program the Spartan 6 on startup from a SPI FLASH device. 8Mbit serial SPI FLASH devices are cheap @<$2ea and could store a multi-configuration. One for 65Org16 core and one for a 6502 core, jumper selectable.

And after configuration, you could copy the rest of the SPI Flash device to SRAM, and execute as program code.

[ElEctric_EyE]

Arlet wrote:

...And after configuration, you could copy the rest of the SPI Flash device to SRAM, and execute as program code.

So you are of the thought that external SRAM is necessary?

[Arlet]

ElEctric_EyE wrote:

So you are of the thought that external SRAM is necessary?

No. It depends on the application, and I assume various interested people have different goals in mind. That said, I'd think that having some external RAM would benefit most projects.

Since the FPGAs have so many IO pins, and the headers take up considerable space, I suggested adding the RAM chip on the FPGA board, seeing that it wouldn't have much impact on the overall board size. Having the RAM close means that the bus is nice and short, and can be made to run at high speeds (say 100 MHz) without much design trouble.

And if you really don't need it, you can always leave the space empty.

[ElEctric_EyE]

I see your point. There are some 256KBx16 10ns SRAMs 44-pin TSOPII out there for ~$6ea. Larger ones like 54-pin TSOPII 1MBx16 10ns are ~$40ea. Even larger ones are in BGA style packages...

I would volunteer my time to start the schematic for this thing, but I will be getting back into the DevBoard very soon. Has anyone started anything for this yet?

[BigEd]

I've added a poll to this thread - not even slightly binding but would be interesting to know what the actual level of interest is. I would imagine the cost of the board would be costs plus shipping plus some margin for lossage - make some reasonable assumption.

The way these things usually go, the cost of the PCB depends so much on the quantity that the number of orders becomes the biggest factor in determining the price.

I imagine this would be done in the USA, so factor that into the projected and completely speculative shipping cost.

Cheers
Ed

[Dajgoro]

What about making it similar to a 68k, it has 64 pins, and 64 pin dip socket are kinda common...

[GARTHWILSON]

64-pin DIPs don't perform well at so many MHz. Otherwise, yes, it would be great to make a board that size with pins to essentially make it a DIP. Interplex makes the pins you clip on the edge of the PC board and solder to make it functionally like an IC.

[BigEd]

There's a bit of a downside to 64pins, in that it doesn't allow for a full-on 65Org32, but setting that to one side:

A board with a double row of 64 pins, for 128 pins, could allow for the inner row to be populated for a 64-pin DIL low-speed (or high-risk!) interface, or both rows to be populated to add shielding for improved integrity.

It's looking like a board with options to be populated in different ways will be best, because that allows for a higher quantity of boards. It also keeps happy those people who want to get soldering. In fact, selling kits of board plus pre-programmed FPGA plus some subset of other necessary components might be a good way to proceed: with soldered-up boards at a higher price if the seller (and buyer) agreed on that. (On the [cosmacelf] list, a kit of parts is $90 and the unusual step of buying an assembled kit is an extra $50. No-one complained at the price or the offer, so evidently that's felt to be fair over there. Whether anyone pays the extra is another question.)

What's novel about this idea is two-fold: a 65Oorg16 for people who are not yet ready to program FPGAs themselves, and, possibly, an FPGA breakout board with specifically the features we think we want. (But not necessarily a very cheap one, if we keep adding features and/or size.)

To be clear, though: the FPGA would be re-programmable by anyone who is ready to do so.

Cheers
Ed