Very slow day at work today...
Gave me a chance to work on the clocks. I didn't have to use DCM's after all. I used 1 of the 2 PLL's present in the Spartan 6 144-pin QFP package.
I had to work with the verilog model as the IPCore generator was giving me problems trying to implement the resultant .xco file in a schematic.
So it did pass synthesis, and it looks good in ISim generating the 12MHz and 27MHz from the 100MHz in. The necessary constraints are at the bottom. I'll report back after real world testing...
I have to keep the disclaimer attached for legal reasons.
Code: Select all
// file: clkgen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____27.000______0.000______50.0______404.437____249.435
// CLK_OUT2____12.000______0.000______50.0______472.078____249.435
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clkgen,clk_wiz_v3_2,{component_name=clkgen,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clkgen
( input CLK_IN1,
output CLK_OUT1,
output CLK_OUT2 );
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT (27),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (20),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (45),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (10.000),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
endmodule
Constraints to make it pass synthesis, and add pin #'s, volts, etc.
Code: Select all
NET "MAINCLK" IOSTANDARD = LVCMOS33;
NET "VIDEOCLK" IOSTANDARD = LVCMOS33;
NET "USBCLK" IOSTANDARD = LVCMOS33;
NET "MAINCLK" LOC = P123;
NET "VIDEOCLK" LOC = P92;
NET "USBCLK" LOC = P23;
PIN "XLXI_4/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; //get it to pass a strict synthesis
PIN "XLXI_4/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; //get it to pass a strict synthesis
NET "MAINCLK" TNM_NET = "MAINCLK";
TIMESPEC TS_MAINCLK = PERIOD "MAINCLK" 10 ns HIGH 50 %;
XLXI_4 is the name of the symbol created from the clkgen.v.
This is the HDL translation of the very simple top_level schematic assigning I/O pins to the design:
Code: Select all
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.2
// \ \ Application : sch2hdl
// / / Filename : top_level.vf
// /___/ /\ Timestamp : 09/08/2011 19:15:07
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family spartan6 -verilog C:/USB/top_level.vf -w C:/USB/top_level.sch
//Design Name: top_level
//Device: spartan6
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module top_level(MAINCLK,
USBCLK,
VIDEOCLK);
input MAINCLK;
output USBCLK;
output VIDEOCLK;
clkgen XLXI_4 (.CLK_IN1(MAINCLK),
.CLK_OUT1(VIDEOCLK),
.CLK_OUT2(USBCLK));
endmodule
