// file: clkgen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____27.000______0.000______50.0______404.437____249.435
// CLK_OUT2____12.000______0.000______50.0______472.078____249.435
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clkgen,clk_wiz_v3_2,{component_name=clkgen,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clkgen
 (  input         CLK_IN1,
    output        CLK_OUT1,
    output        CLK_OUT2   );

  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));
   
  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        locked_unused;
  wire        clkfbout;
  wire        clkout2_unused;
  wire        clkout3_unused;
  wire        clkout4_unused;
  wire        clkout5_unused;

  PLL_BASE
  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("INTERNAL"),
    .DIVCLK_DIVIDE          (5),
    .CLKFBOUT_MULT          (27),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (20),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKOUT1_DIVIDE         (45),
    .CLKOUT1_PHASE          (0.000),
    .CLKOUT1_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (10.000),
    .REF_JITTER             (0.010))
  pll_base_inst
 
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1),
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    .LOCKED                (locked_unused),
    .RST                   (1'b0),
   
     // Input clock control
    .CLKFBIN               (clkfbout),
    .CLKIN                 (clkin1));
 
 // Output buffering
//-----------------------------------

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));


  BUFG clkout2_buf
   (.O   (CLK_OUT2),
    .I   (clkout1));

endmodule

NET "MAINCLK" IOSTANDARD = LVCMOS33;
NET "VIDEOCLK" IOSTANDARD = LVCMOS33;
NET "USBCLK" IOSTANDARD = LVCMOS33;

NET "MAINCLK" LOC = P123;
NET "VIDEOCLK" LOC = P92;
NET "USBCLK" LOC = P23;

PIN "XLXI_4/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; //get it to pass a strict synthesis
PIN "XLXI_4/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; //get it to pass a strict synthesis

NET "MAINCLK" TNM_NET = "MAINCLK";
TIMESPEC TS_MAINCLK = PERIOD "MAINCLK" 10 ns HIGH 50 %;

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 13.2
//  \   \         Application : sch2hdl
//  /   /         Filename : top_level.vf
// /___/   /\     Timestamp : 09/08/2011 19:15:07
// \   \  /  \
//  \___\/\___\
//
//Command: sch2hdl -intstyle ise -family spartan6 -verilog C:/USB/top_level.vf -w C:/USB/top_level.sch
//Design Name: top_level
//Device: spartan6
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be
//    synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps

module top_level(MAINCLK,
                 USBCLK,
                 VIDEOCLK);

    input MAINCLK;
   output USBCLK;
   output VIDEOCLK;
   
   
   clkgen  XLXI_4 (.CLK_IN1(MAINCLK),
                  .CLK_OUT1(VIDEOCLK),
                  .CLK_OUT2(USBCLK));
endmodule

wor [15:0] bus;

module ORs( INA,
            INB,
            INC,
            IND,
            INE,
            INF,
            DO);

    input [15:0] INA;
    input [15:0] INB;
    input [15:0] INC;
    input [15:0] IND;
    input [15:0] INE;
    input [15:0] INF;
   output [15:0] DO;
   
   
   wor [15:0] INA;
       [15:0] INB;
       [15:0] INC;
       [15:0] IND;
       [15:0] INE;
       [15:0] INF;
       //[15:0] DO;
 
  endmodule

wire [15:0] do;

mem mem0( .DO(do),  ... other ports... );

wor [15:0] do;

mem mem0( .DO(do),  ... other ports... );
mem mem1( .DO(do),  ... other ports... );

module ORs(   INA,
            INB,
            INC,
            IND,
            INE,
            INF,
            DO );
             
   input [15:0] INA;   
   input [15:0] INB;
   input [15:0] INC;
   input [15:0] IND;
   input [15:0] INE;
   input [15:0] INF;
  output [15:0] DO;
 
  wor [15:0] DO;
 
  endmodule