I assume they wanted to provide larger memory for the time, using dRAM and an internal dRAM controller instead of SRAM, but with an SRAM like interface. Not sure if that ever was a viable business. But they existed, and I saw them in my ancient Hitachi Memory handbook...
André
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/
Has anyone experienced or heard of problems when accessing fast memory slowly? Such as 20-55nS sram being accessed with 500nS /CE?
SRAM means “static random-access memory.” The key word here is “static,” which means the RAM merely responds to input signal states (low or high), without regard to the passage of time. Ergo there should never be a problem with slow access, as long as you operate within the recommended DC specs, e.g., VIL, VIH, etc., observe the input setup and hold times, and input signal transition rates are within spec.
This explanation is completely wrong.
Dynamic RAM stores data using an electrical charge in a capacitor which leaks. The data degrades over time and must be refreshed.
Static RAM stores data in flip-flops, so the data is static.
