Something to inspire - a fast modern 6809 in verilog

[BigEd]

This BSD-licensed project by Kevin Phillipson, Michael Rywalt and more looks very interesting - a pipelined 6809 architecture, built and tested. I imagine it could be mutated and subsetted into a similarly impressive 6502.

Turbo9 - A Compact & Efficient Pipelined 6809 Microprocessor IP

From the README, some YouTube videos
Turbo9 - Pipelined 6809 - Overview & uRTL Presentation (presentation at VCF SW)
Turbo9 - Pipelined 6809 - Benchmarking & Performance
Turbo9 - Pipelined 6809 - Verification & Design Update (Aug 2021)
Turbo9 - Pipelined 6809 - Introduction & Overview

Also from the README
External shared Program/Data Bus
Adjustable pipeline stages w/ automatic latency adjustment
Different bus configurations available:
Turbo9: 8-bit shared data/program bus
Turbo9S: 16-bit aligned shared data/program bus
Turbo9R: 16-bit non-aligned shared data/program bus
Turbo9GTR: 16-bit non-aligned dual data & program bus

Microcode is compiled directly to gates, not ROMs

microarchitecture diagram

[Yuri]

Interesting, I'll have to dig into that. I kinda wanted to build my own 16-bit CPU, so I'm wondering if they have good docs that I could use to help me with my design.

[enso1]

Has anyone tried to build it? I haven't found info re how big an FPGA it requires...

I am a fan of the 6809 (from afar, never coded in assembly for it myself yet, and BASIC on a TRS-80 Color Computer in 1983 does not really count as coding for the 6809...).

The U register (user stack!) is just such a nice thing to have for Forth!

[AndrewP]

This is very, very cool. I'm slowly watching my way through the presentations and I'm finding them extremely interesting. I do wish I could see where he was pointing on his slides whilst the slide is shown but mostly I can work it out.

Someone (Drogon?) posted a thread asking where to in terms of the next step for hobbyist processors and the answer seemed to be that really there isn't one. The '816* is where it stops - modern ARM and RISC-V processors seemed to be a step too far. The Turbo9, if turned into an ASIC, would be the next step in my mind. And pretty compatible with this forum too.

I can dream, I can dream...

[EDIT - Something I didn't find to be immediately clear was what the memory address bus width was. It's 16bit. Oh well.]

[enso1]

There is a fascinating repo with a cycle-accurate 6809 core here:https://github.com/cavnex/mc6809

It is also full of somewhat grouchy opinionated commentary mixed in with great implementation and reverse-engineering details. For instance,

Quote:

The CPU core itself resides intentionally in one file. I detest reading other people's designs and trying to sort out dependencies when they've basically thrown a few VHDL or Verilog files over the wall. Despite the reality that I've ended up with a single file of about 4000 lines, if you see something referenced, it's defined somewhere above your current cursor position in the file.

.

Every time I do 16-bit math on the 6502 (quite a bit the last few days), I envy 6809'ers. It was the last great chip of that era.

[BigEd]

Interesting find - also verilog, and BSD licensed, but in this case cycle-accurate. So will have lower performance at a given clock speed. Still, the size and speed on a given FPGA could be interesting. (I notice it was validated in GODIL form - a familiar system for many of us here!)

[rwiker]

Stefany Allaire (of c256foenix fame) has a cycle-accurate 6809 module with a 65c02-compatible pinout: https://c256foenix.com/product/fnx6809/. Maybe not all that interesting from a performance point of view, but might be a fun experiment for other 65c02-based platforms.

Also, Ted Fried (MicroCoreLabs) has a Teensy-based 6809-based replacement: https://microcorelabs.wordpress.com/202 ... -emulator/

[BillG]

As Yoda said, "there is another..."

https://63f09.systella.fr/cpu-63f09/

It is mostly a 6309 which can be switched into 32-bit mode. It can run up to 600 MHz.

[enso1]

I had a hard time getting any useful files from the weird ftp server there... I am a bit suspicious of 600MHz, as I haven't seen anything run that fast on fpgas mortals can afford...

[John West]

It's targeting Artix7, which isn't too unaffordable and can go very fast (if you're careful about the logic depth between flip-flops). The VHDL appears to be written by someone with a decent amount of experience. Without testing it myself, I will accept their word that it can go fast.

To download, you need to give "anonymous" as the user name with no password. And you have to set binary mode because apparently it's still the 1970s. So "binary", "cd 63F09", "get SOC_63F09_20240813.TGZ", "disconnect" and "bye". It has been a long time since I last used ftp.

[enso1]

Thanks, I forgot about binary!