This BSD-licensed project by Kevin Phillipson, Michael Rywalt and more looks very interesting - a pipelined 6809 architecture, built and tested. I imagine it could be mutated and subsetted into a similarly impressive 6502.
Turbo9 - A Compact & Efficient Pipelined 6809 Microprocessor IP
From the README, some YouTube videos
Turbo9 - Pipelined 6809 - Overview & uRTL Presentation (presentation at VCF SW)
Turbo9 - Pipelined 6809 - Benchmarking & PerformanceTurbo9 - Pipelined 6809 - Verification & Design Update (Aug 2021)
Turbo9 - Pipelined 6809 - Introduction & OverviewAlso from the README
External shared Program/Data Bus
Adjustable pipeline stages w/ automatic latency adjustment
Different bus configurations available:
Turbo9: 8-bit shared data/program bus
Turbo9S: 16-bit aligned shared data/program bus
Turbo9R: 16-bit non-aligned shared data/program bus
Turbo9GTR: 16-bit non-aligned dual data & program bus
Microcode is compiled directly to gates, not ROMs
Attachment:
File comment: microarchitecture diagram
turbo9_decode_stage_small.png [ 361.66 KiB | Viewed 961 times ]