open source TUBE interface project

[OwenS]

The standard configuration flash chips for most FPGAs also have a JTAG port. The board generally has them daisy chained, so you can program both using the same JTAG connector.

[kc5tja]

Taken from:
www.oho-elektronik.de/pics/UM_GODIL.pdf

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The FPGA is the only member in the JTAG chain connected to CON2.
The FPGA normally configures from the SPI FLASH devices M25P16 or M25P32 (for debugging JTAG
configuration is always also possible).
The SPI Flash can be programmed via its dedicated programming header CON3.
However indirect programming via the JTAG chain with ISE10.1 (and newer SW) is recommended.

Note that their block diagrams also indicates a 14-pin header and/or 9-pin test header also has SPI connectivity, so you can reflash via the SPI port as well, without touching the FPGA's JTAG.

Generally, since they recommend indirect programming of the flash, I would think the means of programming the EEPROM via the FPGA itself involves two basic steps:

(1) Use the JTAG protocol to bit-bang the SPI port. It would be slow, but it'd work. This will fill the EEPROM image. Then,
(2) Use the JTAG to reset the FPGA, causing it to bootstrap directly off the EEPROM, thus programming the FPGA with your downloaded image.

Otherwise, you'll have to download to the flash directly using the SPI port. While it should be faster in terms of I/O throughput, it likely would take more steps at your programming computer.

[BigEd]

Hi Ruud

Ruud wrote:

I can imagine that other readers consider this as OT

But I'll respond on the forum anyhow: FPGAs and CPLDs are a good story for the things we're trying to do.

Ruud wrote:

something simple like reading the buttons and flashing the onboards LEDs is fine for me.

There's a demo program available from OHO which does that kind of thing, and it might be a good start just to bring that up. The vhdl projects for the DY1 module are what you want - OHO_DY1_GODIL48_103.zip - even if you don't have a DY1. The DY1 is a 3-digit display which sits on (and extends) the 9-pin port on the south edge. The Demo_Dy1.vhd is the top level source file.

Ruud wrote:

"GODIL for dummys" that enables an intelligent dummy like me to start up his first Verilog or VHDL program.

Another possible way to start is to download our beeb816 project files - we've got a few supporting scripts for building projects from the command line. Have a look at tube.20100606T1943.tgz from our Files page - the starting point is the README file in the rtl subdir. If you blindly follow that, you'll get a build directory with some *.sh scripts, one for each stage of the build process.

Ruud wrote:

BTW, I haven't any idea what you use to program the GODIL but FYI, I ordered this USB-JTAG cable.

Good move! I've been using a parallel port cable and it's short and a little unreliable(*actually no - see my next post*). Also, so many computers have no parallel port.

Ruud wrote:

And what software are you using? I presume the ISE Webpack but just to be sure.

Yes, the Webpack. It can perform all the steps: synthesis, simulation, place and route, producing a bitstream for jtag or for an EEPROM. It's huge, and you need to register, those are the only downsides. I recently figured out how to do simulation of a mixed design, so I could have both verilog and vhdl, which is very handy when you're pulling in various other subprojects.

Ruud wrote:

One thing is already confusing me: I know you connect a CPLD directly to a JTAG cable. But in this case the GODIL has these extra IC's, AFAIK the EEPROMs (or whatever) that fill the FPGA with data at start-up. But how are these EEPROMs filed? And what makes the EEPROMs to fill the FPGA with data?

Good questions. You have a choice, both using the same jtag cable: during development you download the bitstream (*.bit file), and then when you're happy you download an EEPROM image (*.mcs file) into the EEPROM. The FPGA modules have a jumper to select whether or not they load from EEPROM at power-up. You make the *.mcs file from the *.bit file using the webpack tools. From the command line, I did

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$ promgen -spi -p mcs -s 16384 -u 0 T65.bit

and it made three files

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Release 11.1 - Promgen L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file
<.../spartan3.acd> with local file
<.../spartan3.acd>
0x29500 (169216) bytes loaded up from 0x0
Using user-specified prom size of 16384K
Writing file "T65.mcs".
Writing file "T65.prm".
Writing file "T65.cfi".

which I could then load, again from the command line, with

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$ impact -batch
attachflash -p 1 -spi "M25P16"
assignfiletoattachedflash -p 1 -file "T65.mcs"
program -e -v -c -spionly -showprogress -p 1

The trick here is that Webpack first downloads an SPI downloader into the FPGA, and that design reads the EEPROM data from the JTAG interface and writes to the EEPROM. You don't have to know about the details of SPI for this. I'm sure there are other ways too.

Ruud wrote:

I did RTFM the GODIL PDF but IMHO it wasn't that helpfull.

It's got a lot of useful info, but it isn't a HOWTO on FPGAs. There are lots of Xilinx docs - big ones - download some of those before you go offline:

• Xilinx data sheet
  user guides for Spartan-3E family
  tutorial PDFs
  online manuals

Cheers
Ed

[ElEctric_EyE]

Also Ruud, try the Xilinx forums. They seem to be very helpful to others with hardware problems and beginners using VHDL. Not sure about Verilog, and I know not many help out with my questions because I still use schematic entry...
Is your end goal to put a 6502 on FPGA?

[BigEd]

Couple of things to add: this page has links to pdf and some video for versions 12 and 11 of xilinx webpack. Near the pdf collections there's a wtut_ver.zip archive which contains a worked example of a stopwatch in verilog.

Also, I found that my problems with the parallel cable which made me think it was unreliable were down to the choice of commands I was using to do the programming. I'd picked up 'addDevice' from a xilinx webpage - it turns out that 'assignFile' works better.

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setmode -bscan
setcable -p parport0
assignFile -p 1 -file T65.bit
program -v -p 1

(*edit: got completely confused about navigating xilinx site)

[Ruud]

BigEd wrote:

I loaded the T65 free 6502 design and got some 6502-like activity on the pins,

I'm able to program my Godil now: I found out I made a silly mistake some where. Now I need to learn VHDL (again). My question: could I have VHDL or whatever is needed, please? Learning VHDL won't be the problem IMHO but I haven't any idea how to connect software and hardware yet in this case.

FYI: I found an ISA card with four 8255 on it, giving me 96 I/O lines. The idea is to connect the Godil with these I/O lines. The Godil can serve as a CPU for a system emulated by the PC. IMHO in this way I can test the Godil for any known CPU with up to 48 pins. OK, it won't be real time but that shouldn't be a problem IMO.

[kc5tja]

From my last experience working with FPGAs at Hifn, the JTAG interface on the FPGA itself is used to bit-bang the EEPROM pins to program it. Thus, you're literally going through the FPGA itself to program the EEPROM. The synthesis software needs to know the kind of FPGA you're programming, so it can bit-bang the right bits, and also to generate the image to store in the EEPROM.

The other questions are best answered by those with more direct experience than I.

[BigEd]

Ruud wrote:

BigEd wrote:

I loaded the T65 free 6502 design and got some 6502-like activity on the pins,

I'm able to program my Godil now: I found out I made a silly mistake some where. Now I need to learn VHDL (again). My question: could I have VHDL or whatever is needed, please?

Hi Ruud
I'm not certain right now of the license on the T65, so it's best to fetch it direct from the pacedev project. They made the most recent fix I can find (there are 3 versions of the T65 in various places) which is a fix to the dreaded B flag.

Two methods I've just verified:

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wget --no-check-certificate -r -nd -P T65 -np https://svn.pacedev.net/repos/pace/sw/src/component/cpu/t65/

or

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svn co https://svn.pacedev.net/repos/pace/sw/src/component/cpu/t65 T65

where you'll need to confirm that you want to accept the self-signed certificate.

In both cases you should get a subdir called T65 with contents like this

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  7783 2008-01-08 07:36 T65_ALU.vhd
 25902 2008-01-14 01:52 T65_MCode.vhd
  4716 2008-01-08 07:36 T65_Pack.vhd
 16314 2009-02-11 14:24 T65.vhd

although the wget method will preserve the timestamps (as above) and give you a bonus index.html.

There's probably useful info about T65 on opencores which has an older version of the sources, and also might be useful info at fpgaarcade which again has an old version, but inside it there's an even older version, which has some additional files (SRAM, UART) and some simulation and synthesis support files.

Cheers
Ed

[Ruud]

Hallo Ed,

Ruud wrote:

My question: could I have VHDL or whatever is needed

WOW, I don't know what went wrong here. I meant to say: "could I have your VHDL version of T65 or whatever is needed".