Hi Ruud
Ruud wrote:
I can imagine that other readers consider this as OT
But I'll respond on the forum anyhow: FPGAs and CPLDs are a good story for the things we're trying to do.
Ruud wrote:
something simple like reading the buttons and flashing the onboards LEDs is fine for me.
There's a
demo program available from OHO which does that kind of thing, and it might be a good start just to bring that up. The vhdl projects for the DY1 module are what you want - OHO_DY1_GODIL48_103.zip - even if you don't have a DY1. The DY1 is a 3-digit display which sits on (and extends) the 9-pin port on the south edge. The Demo_Dy1.vhd is the top level source file.
Ruud wrote:
"GODIL for dummys" that enables an intelligent dummy like me to start up his first Verilog or VHDL program.
Another possible way to start is to download our beeb816 project files - we've got a few supporting scripts for building projects from the command line. Have a look at tube.20100606T1943.tgz from our
Files page - the starting point is the README file in the rtl subdir. If you blindly follow that, you'll get a build directory with some *.sh scripts, one for each stage of the build process.
Ruud wrote:
BTW, I haven't any idea what you use to program the GODIL but FYI, I ordered this USB-JTAG cable.
Good move! I've been using a parallel port cable and it's short and a little unreliable(*actually no - see my next post*). Also, so many computers have no parallel port.
Ruud wrote:
And what software are you using? I presume the ISE Webpack but just to be sure.
Yes, the Webpack. It can perform all the steps: synthesis, simulation, place and route, producing a bitstream for jtag or for an EEPROM. It's huge, and you need to register, those are the only downsides. I recently figured out how to do simulation of a mixed design, so I could have both verilog and vhdl, which is very handy when you're pulling in various other subprojects.
Ruud wrote:
One thing is already confusing me: I know you connect a CPLD directly to a JTAG cable. But in this case the GODIL has these extra IC's, AFAIK the EEPROMs (or whatever) that fill the FPGA with data at start-up. But how are these EEPROMs filed? And what makes the EEPROMs to fill the FPGA with data?
Good questions. You have a choice, both using the same jtag cable: during development you download the bitstream (*.bit file), and then when you're happy you download an EEPROM image (*.mcs file) into the EEPROM. The FPGA modules have a jumper to select whether or not they load from EEPROM at power-up. You make the *.mcs file from the *.bit file using the webpack tools. From the command line, I did
Code:
$ promgen -spi -p mcs -s 16384 -u 0 T65.bit
and it made three files
Code:
Release 11.1 - Promgen L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<.../spartan3.acd> with local file
<.../spartan3.acd>
0x29500 (169216) bytes loaded up from 0x0
Using user-specified prom size of 16384K
Writing file "T65.mcs".
Writing file "T65.prm".
Writing file "T65.cfi".
which I could then load, again from the command line, with
Code:
$ impact -batch
attachflash -p 1 -spi "M25P16"
assignfiletoattachedflash -p 1 -file "T65.mcs"
program -e -v -c -spionly -showprogress -p 1
The trick here is that Webpack first downloads an SPI downloader into the FPGA, and that design reads the EEPROM data from the JTAG interface and writes to the EEPROM. You don't have to know about the details of SPI for this. I'm sure there are other ways too.
Ruud wrote:
I did RTFM the GODIL PDF but IMHO it wasn't that helpfull.
It's got a lot of useful info, but it isn't a HOWTO on FPGAs. There are lots of Xilinx docs - big ones - download some of those before you go offline:
Cheers
Ed