viridi wrote:
I see a switch in the schematic but it is not tied to Vcc anywhere.
Right. VCC and GND go to the supply pins of the inverter IC (as Yuri said), but in this circuit they don't attach to the switch.
It's maybe best to start by pointing out that the two inverters are connected to act as a memory (aka, a flip-flop). If the output happens to be high then it will stay high, and if it happens to be low then it will stay low. This is shown below.
Attachment:
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When the other components are added we can see that the capacitor will slowly (ie; about 50 ms, because of the large resistance) charge or discharge until it is
in the opposite state compared to the input of the first inverter.
And the circuit will remain in this condition until the button is pushed.
Attachment:
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When the button is pushed, the high or low state of the capacitor gets applied to the input of the first inverter, causing the memory aka flipflop to go high if it was low, or go low if it was high. (The cap momentarily overpowers the influence of the 47K resistor; then the flip-flop changes state and the resistor no longer needs to be overpowered.)
Now the capacitor and the input of the first inverter are in agreement rather than opposition. The cap won't appreciably charge or discharge because during this time it is influenced primarily by the small, 47K resistor. But when the button is
released, then the large, 470K resistor will
slowly cause the capacitor to update until it's once again in opposition, ready for the following button-push. And this slowness is what gives the circuit its immunity to contact bounce.
BTW the inverter needs to be a CMOS type (ie, from the 74HC family, for example, NOT 74LS etc). An ordinary 74HC04 will work reasonably well, but on a tiny minority of button-pushes the circuit might falter. If that's not tolerable then use a 74HC14, for example, whose Schmitt trigger feature will ensure that output transitions always have crisp rise and fall times.
-- Jeff
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