There's also the Gigatron. I seem to recall that there was some interesting work done getting it to run 6502 code.

https://gigatron.io

Hello bmab, and welcome.
Sorry for my delayed response.

If you are out to build a TTL implementation of the original 6502 architecture,
please be aware that you are out to stumble into a nice adventure which could take 3+ years.

When Drass, Jeff (Dr Jefyll) and me did the C74 project,
we did not know as much about the architecture of the ariginal 6502 core as we know now.
So the C74 core has a different architecture than the original 6502 core, that's also because we deliberately aimed at speed.

I think your best bet is reading the 6509 dissection.
At logic design level the 6509 core is pretty much identical to the 6502 core,
at transistor level there is a little difference in the clock generation for the control latches which IMHO doesn't matter much.

6509 basically is 6502 plus sort of a crude MMU which gives you 4 additional address lines.

Hello everyone!

I found this project here:

http://forum.6502.org/viewtopic.php?f=12&t=5811

I'm doubt about architecture. Is it correct for a 6502?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The word "architecture" can mean different things to different people. For example, if someone built a project that can properly execute 6502 code, then that might be considered correct. (In other words, the programmer can't tell the difference between the project and an actual 6502.)

But other folks might not be satisfied unless -- in addition to executing 6502 code -- some or all of the project's implementation details are the same as a 6502... details such as the project's arrangement of ALU's and internal buses, for example. Using that definition, then the C74 project would not be considered correct. (But that doesn't bother us in the slightest! )

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

For the record, that block diagram appears here on the third page of JuanGg's thread "Micro programmed 6502-like CPU". The block diagram comes after the project has passed Klaus' test suite, so it is something which works.

Notably, there's no sign of a temporary data register - that's something which often turns up in re-implementations. Then again, it's only a diagram, not the actual machine. Although Juan hasn't visited here for a long time, it's good to see a project reach a successful conclusion!

(Garth, I believe you misread the diagram - there are not two ALUs, but two registered inputs to a single ALU)

Edit: I should add, one can consider several levels of exactitude in a rebuild: that all official opcodes have the right function, that all official opcodes take the same number of clock cycles as the original, that all official opcodes make the same accesses in the same order as the original... and then there are the undocumented opcodes, which for some parts of 6502 fandom are also important.

Edit: In Juan's case, there's a deliberate omission of decimal mode - a fairly common choice.

I decided to follow this block diagram found in C74 project and its successor TTL 6502 Here I come (2015) and I haven't read all articles about both project, the questions:

Why this block diagram C74 project have a lot of registers in compare with the 6502 block diagram?

What modifications in C74 project we did to aim at speed?

The leftmost quarter or so of the block diagram at https://c74project.com/block-diagram/ appears to be entirely concerned with supporting some of the 65C816 functionality, such as 24-bit addressing and what looks to me like a B register.

There's a lot to read! And the design we ended up with is more complex than the design Drass presented at the beginning of the "TTL 6502 Here I Come" thread. Perhaps you will be interested in this evolution. It took about 3 years!

BTW, this project is the same one described at the C74 project link. You may enjoy this video of a presentation about C74 by Drass at this event.

(The successor to C74 has not yet been built, and may perhaps never be, but the plans are quite far advanced; see 100MHz TTL 6502: Here we go! )

Hmmm. When you drive a car, it is basically the same experience regardless of the engine. For example, it doesn't matter whether the engine has 4, 6 or 8 cyclinders, or whether the engine powered by gasoline, diesel or even electricity.

My point is, there can be various methods that all accomplish the same thing.

-- Jeff

ps- Sean is correct about the added features. However, even without those added features, the C74 block diagram still does not match that of an actual 6502. For example, the C74 uses microcode rather than a PLA. This is one reason there are more registers -- for example, the pipeline registers, which are not visible by the programmer. ETA: oops, they're also not shown in that diagram!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

About the "extra" registers - I don't know the C74 in detail, but it's worth noting
- there's more storage in a CPU than the programmer-visible registers
- a "register" in NMOS technology may need as little as one transistor per bit using the design style seen in the 6502 which means it takes up minimal space - at least, when "register" is allowed to include "transparent latch"

In this sense, the 6502 ALU has registers on both inputs - but you don't always see those in a block diagram.

But it may be that the "extra" registers you are seeing relate to extra functionality, as Jeff notes.

It's been a while, and I don't remember too much of the details...

Original C74 block diagram:


Tried to mark the parts which you probably won't need in orange:

Address Bus Bit 16..23: only 65816 has 24 Bit address bus, NMOS 6502 and 65C02 have 16 Bit address bus.
Anything labeled "UFO" is support for illegal NMOS 6502 instructions (which were "UnFOrseen by the original NMOS designers", long story).
65C02 has STZ instruction, while NMOS 6502 has not.
BCG (Bitwise constant generator) is support for the Rockwell R65C02 Bit testing/manipulation instructions (NMOS 6502 and non_Rockwell 65C02 lack them).

This might be of interest (DrMattRegan's SAP-6502 series)