A (Win)COUPL of Questions - ATF1504AS PLC44

[plasmo]

You need TL866II Plus to program ATF22V10. It has no JTAG so can’t program with ATF150x programmer.

ATF1502 has 32 macrocells instead of 64 macrocells of ATF1504. It should be enough for address latches and address decodes.
Bill

[Jmstein7]

plasmo wrote:

You need TL866II Plus to program ATF22V10. It has no JTAG so can’t program with ATF150x programmer.

Oh! My EEPROM programmer!

Phew! So, I can use XGPro?

Jonathan

[BigDumbDinosaur]

Jmstein7 wrote:

I saw ProChip Designer on the Microchip site, when I was getting WinCUPL and ATMISP. Is that any good? It seems to permit the use of HDL, though I guess you have to buy a license if you want to synthesize anything? Doesn't that sort of render it useless?

I had looked into getting ProChip Designer some years ago and passed.  It’s quite expensive, although very capable.  If I were professionally designing programmable logic, I’d buy it, but definitely not for hobby use.

Quote:

EDIT: I was just browsing on Mouser and I saw the following:
ATF750C-7PX
ATF750C-7JX
ATF1502AS-7JX44

The last one being a "cut down" version of the one I'm using (but 7.5ns)

The ATF1502AS-7JX44 is a 32-macrocell version of the ATF1504AS-7JX44.  Even with only 32 MCs, the 1502 is much more capable than a GAL.  That said, I still recommend you do your first build with a GAL to get your feet wet—unless you are going to build your unit with extended RAM, in which case using a CPLD would be a better choice.

I do not recommend using the ATF750, or its big brother, the ATF2500.  Both devices are basically oversized GALs with a hinky programming algorithm that few programmers are able to support.  I’m not even sure why Microchip produces these things, considering that their smallest CPLD, the ATF1500AS, has more capability and is inexpensive.  Also, the 150x series has JTAG, which the ATF750 and ATF2500 do not have.

Quote:

Do these have enough to demultiplex the Bank Addresses from the Data lines, while also decoding addresses?

Yes.  You will be more constrained by the number of available I/O pins than the logic capacity.

Speaking of demuxing the bank bits, that is a task better performed in a CPLD than a GAL, in my opinion.  Setting up transparent latches in CUPL is pretty simple with a CPLD when using buried logic...

Code: Select all

pinnode   = extram;     /* extended address latch */

extram.LE = PHI1;       /* open bank latch        */
extram.L  = PHI1 & D0;  /* capture A16 on Ø2 low  */

A16       = extram;     /* drive A16              */

The above is an example that latches A16 from D0—it would be used in a system with 128 KB of RAM.  The PINNODE statement declares extram to be a buried node. The extram.LE and extram.L statements tell CUPL that the extram node is a transparent latch.  extram.LE opens the latch when PHI1 is true (PHI1 is the inverted Ø2 clock signal), and extram.L is the latch itself.

The above arrangement works on the same principle as a discrete latch, such as a 74AHC573.  Note that if you are going to use a bus transceiver on the 816’s data bus, the DO signal must be derived from the 816 side of the transceiver, since the transceiver will be in the high-Z state during Ø2 low.

The preceding code may be expanded to work with more RAM with some minor changes...

Code: Select all

pinnode         = [extram3..0];  /* bank bit latches   */

[extram3..0].LE = PHI1;          /* open latches on Ø1 */
[extram3..0].L  = [D3..0];       /* capture A16-A19    */

[A19...16]      = [extram3..0];  /* drive A16-A19      */

The above would be support a system with 1 MB of RAM.

Quote:

I looked at the datasheet for the ATF750Cs, and there is nothing about programing them.

Supposedly, the 750 is programmed the same as a GAL.  However, it seems to be a device that is not well-supported by device programmers.  I suspect the algorithm is the same as for Microchip’s other GALs.  YMMV.

[Jmstein7]

BigDumbDinosaur wrote:

The ATF1502AS-7JX44 is a 32-macrocell version of the ATF1504AS-7JX44.  Even with only 32 MCs, the 1502 is much more capable than a GAL.  That said, I still recommend you do your first build with a GAL to get your feet wet—unless you are going to build your unit with extended RAM, in which case using a CPLD would be a better choice.

I picked up some 7.5s from DigiKey. I'm going to be using the memory space above 64k, so it seemed like a good idea, as you said.

Quote:

Quote:

Do these have enough to demultiplex the Bank Addresses from the Data lines, while also decoding addresses?

You will be more constrained by the number of available I/O pins than the logic capacity.

I'm surprised that there is no 84 pin version of the faster one (7.5ns). It goes right from 44 to 100 pins, though there is an 84 pin one at 10ns.

Quote:

Speaking of demuxing the bank bits, that is a task better performed in a CPLD than a GAL, in my opinion.  Setting up transparent latches in CUPL is pretty simple with a CPLD when using buried logic...

Code: Select all

pinnode   = extram;     /* extended address latch */

extram.LE = PHI1;       /* open bank latch        */
extram.L  = PHI1 & D0;  /* capture A16 on Ø2 low  */

A16       = extram;     /* drive A16              */

The above is an example that latches A16 from D0—it would be used in a system with 128 KB of RAM.  The PINNODE statement declares extram to be a buried node. The extram.LE and extram.L statements tell CUPL that the extram node is a transparent latch.  extram.LE opens the latch when PHI1 is true (PHI1 is the inverted Ø2 clock signal), and extram.L is the latch itself.

The above arrangement works on the same principle as a discrete latch, such as a 74AHC573.  Note that if you are going to use a bus transceiver on the 816’s data bus, the DO signal must be derived from the 816 side of the transceiver, since the transceiver will be in the high-Z state during Ø2 low.

The preceding code may be expanded to work with more RAM with some minor changes...

Code: Select all

pinnode         = [extram3..0];  /* bank bit latches   */

[extram3..0].LE = PHI1;          /* open latches on Ø1 */
[extram3..0].L  = [D3..0];       /* capture A16-A19    */

[A19...16]      = [extram3..0];  /* drive A16-A19      */

The above would be support a system with 1 MB of RAM.

It's really amazing how flexible these things are; can really get down into the nitty gritty details and configuration options.

Jonathan

[plasmo]

Jmstein7 wrote:

It's really amazing how flexible these things are; can really get down into the nitty gritty details and configuration options.
Jonathan

ATF1502 is pin-compatible with ATF1504, in fact it is also pin compatible with EPM7032S and EPM7064S. Doing address decodes and data latches, you won't have problem with smaller ATF1502, but if you decided to have more complex functions like internal ROM, serial port, I2C, etc, then you can always get the larger ATF1504 without changing the PCB design.

PCB manufacturers produce 10 pc boards for $5, so I have a design idea with CPLD that allows 10 different functions by changing CPLD designs and moving some jumpers around.
Bill
PS, W65C02 and W65C816 are so similar physically, you can easily accommodate both on the same PCB by changing CPLD equations.

[Jmstein7]

plasmo wrote:

ATF1502 is pin-compatible with ATF1504, in fact it is also pin compatible with EPM7032S and EPM7064S. Doing address decodes and data latches, you won't have problem with smaller ATF1502, but if you decided to have more complex functions like internal ROM, serial port, I2C, etc, then you can always get the larger ATF1504 without changing the PCB design.

PCB manufacturers produce 10 pc boards for $5, so I have a design idea with CPLD that allows 10 different functions by changing CPLD designs and moving some jumpers around.
Bill
PS, W65C02 and W65C816 are so similar physically, you can easily accommodate both on the same PCB by changing CPLD equations.

Just out of curiosity, where do you order your PCBs from? I've used JLCPCB, and it got really expensive, really fast.

Jonathan

[drogon]

Jmstein7 wrote:

Just out of curiosity, where do you order your PCBs from? I've used JLCPCB, and it got really expensive, really fast.

Jonathan

Can't speak for others but I use JLCPCB myself and they're cheap enough - last lot I ordered was 5 PCBs of 100x100mm - I paid extra for expedited manufacture and expedited delivery and got them from China to the UK in 5 days for £30. I could have saved a bit over £10 if I hadn't been desperate to get them before xmas.

PCBway seems a viable alternative though - and I often see many online creators use them via sponsorship deals, etc. (and I have a sponsorship deal if I want it, but no active projects). So it might pay to shop around - and of-course where you are in the world will hugely influence where/who you buy from.

However - also consider what you're getting - could I have envisaged 5 PCBs for that price even 20 year ago? No way. And that's the issue - things like the Raspberry Pi being almost too cheap have forced everyone into a race to the bottom of the barrel.

-Gordon

[Proxy]

I also use JLCPCB. they're very affordable.
going FAR above 10x10cm gets expensive fast. so you want to try and compact things as much as possible or if you actually have that many components that it cannot be made more compact, break it into multiple PCBs (like having RAM or IO on a seperate card for example).
The largest PCB i ever ordered was my 68k SBC which was 137.2 x 91.4mm and was still only 8.50 EUR.
checking their instant quote thingy, even 15x15cm is only ~11 EUR. so what size were you trying to do that it got to expensive for you?

[Jmstein7]

Proxy wrote:

so what size were you trying to do that it got to expensive for you?

This guy, here

[Jmstein7]

drogon wrote:

However - also consider what you're getting - could I have envisaged 5 PCBs for that price even 20 year ago? No way. And that's the issue - things like the Raspberry Pi being almost too cheap have forced everyone into a race to the bottom of the barrel.

-Gordon

That is a very fair point.

What about your design tools? I've only ever used EasyEDA.

Jonathan

[Proxy]

Jmstein7 wrote:

This guy, here

yea you can definitely squeeze that down by a lot!
one option: you could try to be lazy like me, in your CAD program put all the ICs on the board with around 200-300mils of space between them, make sure the ratsnest isn't too bad, and then let an autorouter like freerouting do the rest.
and if you're wondering about the quality of the routing job, let's just say that both my 65816 and 65C02 boards run at ~20MHz and 99% of the routing was done by the autorouter.

Jmstein7 wrote:

What about your design tools? I've only ever used EasyEDA.

not aimed at me, but still to throw my 2 cents in. i've always been a KiCad guy. like every piece of software it has some quirks and annoyances but overall my experience with it has been pretty damn positive.

[plasmo]

I just sent out 4 designs to JLCPCB, all 100mmx100mm, 20 4-layer boards, 5 2-layer. DHL shipping, $60 total. They all have CPLD which is critical in reducing board size, so are SMT package. Also pack your board as tight as the auto router will handle, and combine multiple designs in one order. This is 100x100mm 68040 with CPLD at back and TQFP-80 quad serial device.
Bill

[Jmstein7]

Proxy wrote:

one option: you could try to be lazy like me, in your CAD program put all the ICs on the board with around 200-300mils of space between them, make sure the ratsnest isn't too bad, and then let an autorouter like freerouting do the rest.
and if you're wondering about the quality of the routing job, let's just say that both my 65816 and 65C02 boards run at ~20MHz and 99% of the routing was done by the autorouter.

Ha! I'm struggling to get past 8mhz! And I'm using 55ns Flash Rom, as the EEPROMs I was using didn't get below 100ns; but, everything is hand soldered. What RAM and ROM are you using to get to 20mhz? I didn't know it was possible to get past 14mhz, or so.

As to autorouter, what does that workflow look like? I HATE routing manually. Hate it. It takes me forever, and I'm always guessing with trace sizes and VIAs and all that. I've also only used double layer PCBs.

Jonathan

[Jmstein7]

plasmo wrote:

I just sent out 4 designs to JLCPCB, all 100mmx100mm, 20 4-layer boards, 5 2-layer. DHL shipping, $60 total. They all have CPLD which is critical in reducing board size, so are SMT package. Also pack your board as tight as the auto router will handle, and combine multiple designs in one order. This is 100x100mm 68040 with CPLD at back and TQFP-80 quad serial device.
Bill

That is very cool.

Like I just asked proxy, what is a good workflow that allows autorouting to do most of the work?

Jonathan

[gilhad]

Yes, I too use KiCad and autorouting - first I try, if it is even possible to route it somehow, then I move the chips around, if I think it could help, then, if I have something in my mind I route it manually (like some bus) and then I let autorouter do the rest.
And then I improve anything I can spot.
Basically artefacts from first phases of routing - strange shaped wires near pads. And aligning corners, setting equivalent distancies between wires and sometimes also changing trace of too long wires.
It is more like cooperation

And I save each step to reload instead of undo.