Generating small signal delays with a 74LVC14 Schmitt gate

[AndrewP]

This is something I've been meaning to test for sometime; and that is how can I delay a signal by a small time, on the order of 3ns to 12ns.

It's not something I really want to do as I'd far rather have my signals gated by some well known and very consistent clock but venturing into the world of SVGA has shown me there are going to be times it's simpler just to delay a signal slightly.

My setup is a 40Mhz clock running into a 74LVC161 counter from there I use the terminal count (TC) pin to generate a nicely spaced signal that I can trigger my scope on. I also use TC as the signal input into a 74LVC14 Schmitt inverter. Everything is running on a breadboard.

With no further ado this is what I found:

[EDIT]Unfortunately I seem to have too many attachments in single post so I'm going to have to split this into several posts. [/EDIT]

[AndrewP]

• A direct connection from the output of inverter one to the input of inverter two gave a 2.3ns delay measured between the input and output of inverter two.

• A 100Ω resistor connected from the output of inverter one to the input of inverter two gave a 3.4ns delay measured between the output of inverter one and output of inverter two.

[AndrewP]

• A 220Ω resistor connected from the output of inverter one to the input of inverter two gave a 4.4ns delay measured between the output of inverter one and output of inverter two.

• A direct connection from the output of inverter one to the input of inverter two followed by a direct connection from the output of inverter two to the input of inverter three gave a 4.2ns delay measured between the output of inverter one and output of inverter three.

[AndrewP]

• A 100Ω resistor connected from the output of inverter one to the input of inverter two followed by a 100Ω resistor connected from the output of inverter two to the input of inverter three gave a 6.1ns delay measured between the output of inverter one and output of inverter three.

• A 470Ω resistor connected from the output of inverter one to the input of inverter two followed by a 470Ω resistor connected from the output of inverter two to the input of inverter three gave a 10.4ns delay measured between the output of inverter one and output of inverter three.

[AndrewP]

Was this particularly rigorous? No

Is this meaningful? Kinda. Measured delays should be viewed with a dose of skepticism as I'm using breadboard and it is quite easy to change a delay by about 1/2 a nanosecond by poking my finger into various wires. I'm also running at a perfect room temperature of 25°C.

Is this useful? Kinda. Even though there will be variances between timings from a breadboard and timings on a PCB I think the general times are not going to get significantly smaller. I noticed that soldering the inverter inputs to the outputs together (for direct connection measurements) on the adapter board had barely any effect at all. I suspect the oscilloscope probe positions (i.e. plugged into a breadboard) and the length of the probe connections have more effect. I also should point out that the inverter outputs are only driving another single inverter input. I will probably need to add a line driver if I'm going to use one of those outputs from several other inputs.

With all that said the gate delay timing I saw falls nicely in between the datasheet's given minimum value of 1ns and typical value of 3.2ns.


And lastly what did the real physical mess actually look like?

[BigEd]

Nice to do some organised experiments and measurements - thanks for sharing your results!

I think, in effect, what you have is an RC delay. It has a predictable driver (one of your gates) and a predictable receiver (the other gate) so that makes it fairly well-controlled. The R is going to be the sum of the driver's effective R (may be different for rising vs falling) and your additional discrete R. The C is going to be the C of the receiver. Plus any R, C, or L contributions from your wiring. The choice of Schmitt will give you some insurance against noise as an input voltage crosses the gate's threshold.

It might be that adding a discrete C would be a help, as a larger C will give less sensitivity to stray C. But both your R and C will be subject to some manufacturing tolerance, as will the characteristics of the particular chips you're using. So, the precise delay you get might vary with each re-implementation of the circuit, which makes it a good circuit for one-off hobby use but a potentially poor choice for mass-production. And in-between for in-between volumes of production.

That said, Acorn did have an RC delay in their BBC Micro, which affects the pixel timing, and they got away with that choice. They also (I think) have an RC delay, in effect, for the RAS and CAS strobes, which is far more critical.

[AndrewP]

My pleasure! Although it's not entirely altruistic, I know if I post here I'm going to pay more attention to what readings I take and where I took them but hopefully this is useful to someone else too

With all of that said I woke up at 3am this morning with an idea on how not to need to use signal delays. For which I obviously wasn't going to go back to sleep again until I'd checked it.

So I did. And my design feels far less fragile for it!

Only I didn't go back to sleep afterwards so now I feel pretty fragile today.

A transfer of fragility if you will.

I'm still vastly happier without using signal delays, it felt like I was setting myself up for a world of pain when I had to debug some randomly slightly shorter than expected pulse. A very context free, handwavey explanation: I can pipeline the calculation of video signals by latching them at the end of the pixel clock where they were calculated and then present them to the monitor at the start of the next clock. As long as I 'pipeline' everything the monitor doesn't care.

Props to the Acorn crowd for getting it right.

[GARTHWILSON]

The RxC delay, followed by a Schmitt-trigger gate, is a technique (that's almost too kind of a word for it) shown in a few places on my site and past posts.  It's valid if you keep a few things in mind.  The "C" part (capacitance), if you're depending on just the IC's input and the circuit traces and maybe a socket, can vary wildly.  The IC's input capacitance spec is usually only for a guaranteed max; and how far below that it is, is anyone's guess.  Any given IC will vary based on temperature and supply voltage.  From one IC to another one of the same kind, there can be significant variations.  If you transfer the circuit to a slightly different layout, there will be variations as well.  Next, since we're depending on the voltage thresholds of the hysteresis of the Schmitt trigger, we have to consider that the specification for those is usually a typical, maybe a minimum, but there's no tight spec to depend on.  The capacitance problem is minimized when you need longer delays gotten by larger capacitances, and you can add a capacitor with a tolerance of 20% or tighter.  Any intentionally added capacitance of, say, 33pF or more should be enough to dwarf the capacitance variations already mentioned.  (That won't work if you want just a few ns of delay though.)  Variations in the size of the hysteresis can be compensated for by making the resistor a trimmer.  Otherwise you might want to look into Data Delay Devices' products, ICs with delay taps, or programmable, or with other options, at https://www.datadelay.com/ .

[SpiradiscGuy]

I'm thinking I will also need a smallish (7-10ns) delay when I get to higher speeds, and using higher speed clock sampling tricks will not be convenient. So I recently bought but have not tested a DS1100Z-20+, which is a relatively cheap chip that has multiple-of-4ns delays up to 20ns. I'd love to hear any thoughts on those who have worked on getting fairly consistent manufacturable delays what their experience with this sort of chip is, or good alternatives. Unfortunately I have a cheap 100MHz scope, so it is a bit beyond me to measure these things properly until I upgrade that.

[GARTHWILSON]

SpiradiscGuy wrote:

I'm thinking I will also need a smallish (7-10ns) delay when I get to higher speeds, and using higher speed clock sampling tricks will not be convenient. So I recently bought but have not tested a DS1100Z-20+, which is a relatively cheap chip that has multiple-of-4ns delays up to 20ns. I'd love to hear any thoughts on those who have worked on getting fairly consistent manufacturable delays what their experience with this sort of chip is, or good alternatives. Unfortunately I have a cheap 100MHz scope, so it is a bit beyond me to measure these things properly until I upgrade that.

Do check out the Data Delay Devices delay chips I linked to above.  As for the 'scope speed, I find that there's almost always a way to do more with a given 'scope than people think you can.  What I would do in this case is put several of your delays in series to give a longer delay time, then divide your measured time by the number of delay devices you have lined up.  You could try different combinations of them to verify results in a matrix.  Keep in mind also that a 100MHz scope doesn't suddenly to blind at 101MHz, but instead the 100MHz number is where its response is approximately 3dB down.  If it's a DSO, sampling rate will have to be taken into account too of course.