BDD has agreed to my republishing some of his schematics for his POC V1 and below are those (partial) schematics with my additions. My modifications to the original design were to the RAM (71256SA) and the serial I/O (65c51). I don't have a RT clock (yet), but I'll add one when I get the basic implementation working. I'll also swap out the 65c51 for an 88c92 for serial I/O.
This shows the various selects and the Read/Write qualification:
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SelectsAndRWQual.jpg [ 324.66 KiB | Viewed 352 times ]
This shows the selects connecting to the memory and ACIA:
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MemoryACIA.jpg [ 433.23 KiB | Viewed 352 times ]
In the diagrams, I've omitted the data, address and serial I/O connections to the RAM and ACIA, but they are connected as well.