Peter Monta has dug some more gold out of the 6502 data collected for visual6502.org - he has now committed mask data, mask graphics and a spice netlist for the 6502 to his FPGA netlist tools project on github.

The effect is that he's going in both directions: deriving a gate-level netlist from the transistors for FPGA purposes(*), and deriving circuit-level information which allows analogue simulation.

I've seen some early traces, but we suspect there are a few tweaks needed to the netlist, so it's too early to post pictures. Hopefully we'll see some public pictures soon. Meantime, you can run your own spice simulation, at the rate of about 16 clock cycles per hour - about 4mHz (not to be confused with 4MHz.)

Cheers
Ed

(*)See also Xor's FPGA core which has a family resemblance.

I was able to run a short test simulation - it took about 30 mins to run through reset and then 20mins to do 10 cycles of instructions.



(Edit - the above have link-rotted but see the attachments.)

Of interest in these traces:

- internal busses only rise to 4V or so due to NMOS threshold drop
- the so-called precharge often fights against pulldowns during phi2 rseulting in an intermediate voltage
- sometimes a bus will rapidly drop by a small voltage as it charge-shares with another bus

Here's what I did:

- downloaded Peter Monta's FPGA-netlist-tools project (using git, or tar, or gzip)
- installed ngspice and gwave
- changed into the masks/6502 subdirectory
- modified the 6502-run.spice file to "tran 10ns 100us"
- modified the 6502-system.spice file to tie the databus to 0xCA
- run spice using "ngspice --batch 6502-run.spice" to produce a file 6502-spice-rawfile.raw
- run gwave with a config file to display the signals and busses I'm interested in (otherwise, drag and drop)

Segher has written up some of his findings on the visual6502 wiki. (Edit: archived link, thanks for noting the link rot)

Edit: uploaded a new image of the waveforms, as the old one had rotted away. You can see the reset signal rising, and the sync signal showing activity. You can also see the voltages on the special bus and internal databus not always being full-rail.

Edit: I realise I can make the simulation datafile available, so anyone can explore the results (presumably using gwave) even without running the simulation. You need 300Mbyte of space and the download is a 165Mbyte zip file:
https://www.dropbox.com/s/b0auj32majmd7 ... a.zip?dl=0

Here are the input files, as tweaked:

(Updated previous post with a link to a zip file, so you can waveform-view without running a simulation)

That link (and the whole 6502 wiki) is unfortunately nonfunctional, but thankfully archive.org captured it; the latest capture was in April 2021:

https://web.archive.org/web/20210405071 ... 2_datapath

Thanks! I've updated my link accordingly.