Chromatix wrote:
The datasheet shows a GATE IN pin, but seems to have no description of it. The block diagram does conspicuously omit /NMI from the inputs to the interrupt block, though.
I have checked the
7501/8501 documentation. It states:
Quote:
A control line is provided (GATE IN) to hold off the R/W line until /RAS makes the transition from low to hi. This prevents the Read line from making an early transition to the write state which would cause an improper Early Write Cycle to occur.
GATE IN - TTL level input, used to gate the R/W line to prevent the R/W line from going low during a read cycle, before RAS and CAS so high (resulting in a Read/Write cycle). Normally connected to the MUX line in a system configuration to synchronize the DRAM memory cycle to the processor clock cycle.
So it is nothing common with NMI.