Hardware:
It uses the same address decoding and 68b50 serial interface as Grant Searle's minimal design. It uses the same memory layout with the exception that where he uses an eprom this has ram; half a 32kB part is used at 0xc000 to 0xffff. The remainder of the memory is the same: 32kB from 0x0000 to 0x7fff and a minimally decoded 68b50 at 0xa000-0xbfff.
The obvious point here is that there is no battery backup: the operating system must be loaded each time from a host computer.
74LV8153 serial to parallel interface chips are used to convert received logic level RS-232 format data (i.e. what comes out of a USB-serial adaptor, and what the 68b50 wants to see) to directly address system memory. This would generally be expected to write to the upper memory block (since a reset vector *must* be written) but there is no reason why a full memory image could not be used.
The 74LV8153 chips are individually addressable with three external pins, so eight can live on the same serial line independently of each other. This design uses four:
- 0x0 - data bus
- 0x1 - address bus low
- 0x2 - address bus high
- 0x3 - control/restart
This is a normal 8 bit, one start, one stop, no parity RS-232 sequence (8-n-1) if the data in the RD-232 packet is crafted correctly: bit 0 must always be high, bits 1-3 contain the address, and bits 4-7 contain either the low or high nibble of the data.
After the second packet has been sent, the output pins on the 74LV8153 are set to reflect the data and a control pin SOUT is taken low for one bit period. This design uses the SOUT pin on the data byte to write the data to the ram.
On manual reset, a flip-flop is set which (a) disables the processor's outputs; (b) forces the processor into reset; and (c) enables the outputs on the 74LV8153s, so they have full control of the memory bus. A write to 74LV8153 at 0x3 resets that flip-flop and enables the processor.
To write a byte of data to the ram, the sequence is (remembering you're transmitting two packets for every memory byte):
- send the low address (0x1)
- send the high address (if necessary i.e. if the page has changed) (0x2)
- send the data (0x0)
- manually reset the board
- send the image one byte at a time as above - don't forget to include the reset vector!
- terminate the process and reset the processor by writing any data to 74LV8153 0x03
Obviously this calls for some data preparation off-stage. I envisage a simple program which can accept an intel hex file and convert it to a binary blob containing the necessary address bytes and including the final reset so that the resulting binary file can simply be pushed through the serial transfer of your choice.
The board is ordered; I'll order the parts in the next day or so.
Neil
, folks can find 
Thanks for very promptly taking the 8153 bootloader idea for a spin and sharing the project with us. 
So... here's a version that could be applicable to the '816, assuming one doesn't need all eight of the extra address lines.
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