Following on from the design discussed here: viewtopic.php?f=4&t=2044 and Jeff's suggestion that a new thread be created, presenting the Neolithic Romless.

Hardware:
It uses the same address decoding and 68b50 serial interface as Grant Searle's minimal design. It uses the same memory layout with the exception that where he uses an eprom this has ram; half a 32kB part is used at 0xc000 to 0xffff. The remainder of the memory is the same: 32kB from 0x0000 to 0x7fff and a minimally decoded 68b50 at 0xa000-0xbfff.

The obvious point here is that there is no battery backup: the operating system must be loaded each time from a host computer.

74LV8153 serial to parallel interface chips are used to convert received logic level RS-232 format data (i.e. what comes out of a USB-serial adaptor, and what the 68b50 wants to see) to directly address system memory. This would generally be expected to write to the upper memory block (since a reset vector *must* be written) but there is no reason why a full memory image could not be used.

The 74LV8153 chips are individually addressable with three external pins, so eight can live on the same serial line independently of each other. This design uses four:

• 0x0 - data bus
• 0x1 - address bus low
• 0x2 - address bus high
• 0x3 - control/restart

To write to an individual 74LV8153 chip, two bytes must be written in sequence, both with the same address. In each case, the serial line idles high and the bit sequence consists of the start bit (low), a second start bit (high), three bits of address data, low bit first, four bits of actual data, low bits first and finally a stop bit (high).

This is a normal 8 bit, one start, one stop, no parity RS-232 sequence (8-n-1) if the data in the RD-232 packet is crafted correctly: bit 0 must always be high, bits 1-3 contain the address, and bits 4-7 contain either the low or high nibble of the data.

After the second packet has been sent, the output pins on the 74LV8153 are set to reflect the data and a control pin SOUT is taken low for one bit period. This design uses the SOUT pin on the data byte to write the data to the ram.

On manual reset, a flip-flop is set which (a) disables the processor's outputs; (b) forces the processor into reset; and (c) enables the outputs on the 74LV8153s, so they have full control of the memory bus. A write to 74LV8153 at 0x3 resets that flip-flop and enables the processor.

To write a byte of data to the ram, the sequence is (remembering you're transmitting two packets for every memory byte):

• send the low address (0x1)
• send the high address (if necessary i.e. if the page has changed) (0x2)
• send the data (0x0)

So to send a complete memory image,

• manually reset the board
• send the image one byte at a time as above - don't forget to include the reset vector!
• terminate the process and reset the processor by writing any data to 74LV8153 0x03

Software:
Obviously this calls for some data preparation off-stage. I envisage a simple program which can accept an intel hex file and convert it to a binary blob containing the necessary address bytes and including the final reset so that the resulting binary file can simply be pushed through the serial transfer of your choice.

The board is ordered; I'll order the parts in the next day or so.

Neil

Looks good, Neil! And regarding the charming 74LV8153 , folks can find here the specific posts within the thread you linked. They'll find the '8153 datasheet included.

I'm impressed by how quickly you're able to seize on a new project idea -- to grab the ball and run with it! Thanks for very promptly taking the 8153 bootloader idea for a spin and sharing the project with us.

Although you've only just gotten started yourself, I hope I won't seem to be crowding you if I suggest a tweak or two. And I may be altering the original mandate, which seems to require just an expedient (ie, quick n dirty) proof of concept.

This first drawing is basically identical to what you posted, but for clarity I moved some things around -- stuff I'll be mucking with later. There is one small change; diode D1 now connects between the cap and Vcc (not between the cap and Gnd), as I suspect you actually intended.
In this second drawing I put two previously unused inverters to work, and was able to eliminate the 74HC74 (which itself was only half used).
Speaking of putting chips to work, it irks me to see U5 (the final '8153) with only one of its outputs connected. Those other outputs are a solution looking for a problem! So... here's a version that could be applicable to the '816, assuming one doesn't need all eight of the extra address lines.
Looking forward to further news of your progress...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Using the top bit of one of the 8153s was my original idea but it wakes up with the pins low, which of course reset the flipflop before it got started. I think your double inverter ff works the other way up; nice catch. It does seem a waste of a chip, and you can't even use it for blinkenlights

Neil

p.s. how do you get inline attachments? Whenever I try it just sticks them all at the bottom... what am I missing?

Yes, with the diode turned around this "flipflop" can accept an active-high signal after memory has been initialized and it's time to say "go"!

And that's a serious issue. (All solutions must be given problems! )

Lots of little ins and outs to learn. And this is one of them. Cheers!

Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This looks very interesting and I certainly do not want to disparage anyone's ideas but I have a question.

Why?

Is it just to see if it can be done? (And yes, that is a totally valid reason)

Even if you had a use case for "all RAM", you would only have to give up a tiny bit of it to include a bootloader and you'd easily get away with a lower chip count. Especially using some form of GAL for glue.

_________________
Bill

Hi Bill. I can't speak for Neil but my own interest does have a certain capricious "for the heck of it" element.

As for chip count, it seems to me one's mileage may vary depending on circumstances. If your project is such that you're already commited to having a UART available, then a small ROM as you suggest is a more attractive proposition, compared with a different scenario where the project doesn't otherwise need a UART -- and you'd need to add one, if I'm understanding the idea properly. And also add a crystal or whatever to act as a clock source for the UART.

In contrast, the '8153 manages to dream up its own clock, which is one of the cool things about it.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I'm glad to hear it Jeff. I've always held the belief that thowing darts is the gateway to profound discovery, especially if you know what you are throwing darts at.

Strictly from my own perspective, my last design (a long time ago, been distracted as of late) had a chip count of 6, including the oscillator

Yes, a UART is one of the count. But isn't a UART a serial to parallel chip with a teeny bit of formality trown in? And add to that a traditional UART is an I and O device. A bit of added functionality.

Yeah, sure. But 2 things .. sometimes the main clock can suffice. If not a crystal these days does not cost any more than any other precision component.

It is indeed a very cool device. Worthy of extensive dart throwing.

_________________
Bill

re Why?

One day I will turn my brain off. Until then, it has a bad habit of seeing interesting ideas and seizing on them... it might be an interesting idea as to how to load a system with an external operation system; maybe how to use a smarter but smaller processor both as a boot loader and an interface; maybe how to build a processor from discrete logic (done three or four of those over the years...)

If Western Digital were to release a version of the 6502 which could execute directly from a serial SPI memory, I'd be first in line...

I cheerfully acknowledge that outside a small number of specialised tasks, there are few things which a 6502 system can do which a more modern microcontroller with ram, flash, and sundry I/O can't do better, faster, and cheaper. But I get to do that in my day job. The 6502 was the second processor I learned how to use, and I used it a lot more than any of the other 8-bit parts available at the time. I regard the instruction set and the speed of the processor with some fondness, and I like the challenge of trying to do something in a constrained environment.

I'm not a fan of programmable logic; I don't have an easy way to program it, I don't like the power most of the parts use, and I don't care to hide the logic away in a black box: I would hope that at least some of my projects are educational if people want to take them that way.

But the big 'why' I suppose is because I'm a hobbiest. For the day job, I use what I'm told and design to specification; in the evenings I can design whatever looks like a good idea at the time...

Neil

Nitpick: Western Digital has nothing to do with this - WDC is Western Design Centre.

I have my own idea about how to set up a ROMless 65xx system, but I'll hold it until I've finished what I'm doing with BASIC.

smaller (and not serious) nitpick, WDC is Western Design Center, not Western Design Centre, atleast that's what it says on their site


man i would be so hyped if WDC were to redo the 65c265 to be more like a modern Microcontroller...
programmable flash, useful amounts of internal Memory, hardware IO controllers for things like SPI, I2C, UART (without needing to use a timer to generate the baudrate), actual 32-bit timers, internal system clock and clock divider so you can run it without an external clock (like AVR chips). and of course have the core run at >20MHz natively, with programmable wait states for external accesses (which i think already exist on the current 65c265).

anyways, sick project! i've never seen this Serial to Parallel IC before.
it's like TI extracted the receiving half of a UART, set it into free-run mode, and put it into it's own chip.
acording to the datasheet it has a maximum "data rate" of 24kbps. though i don't know how to intepret that.... is it the rate of actual data you transfer (4 bits of data for 10 bits of packet), or the raw amount of bits it can handle per second (baud rate), if it's the latter then 19200 is the highest standard baud rate it would officially handle.

though i guess speed is not really that much of a concern when all they do is boot the SBC.

but why stop at just one? if you're able to reset and boot the board over UART, and the SBC itself also has a UART (or ideally a DUART), then couldn't you just daisy chain them to create a basic network of 6502's? (with the first one in the chain being connected to a PC or similar self-booting system)

but for that to fully work, the UART connection to the 8153's should go through a demux IC, so by default it points to the 8153's, and after the boot process is done and the CPU is executing code, it can write to some onboard register to manually switch the demux to point to the receiving side of the onboard (D)UART instead.
that way you only need 1 combined UART header, and after booting it turns into a regular bi-directional UART interface. or rather 2 headers, one for the combined booting/regular UART, and one for the other regular UART.

the reason i would have the CPU do the switching manually is so that you cannot accidentally put the board out of booting mode without the CPU running valid code first.

also then i would include some onboard LEDs, because everything network related needs fancy blinking lights

anyways, again interesting project, was just throwing my 2 cents into it.

I've assumed that that's the maximum bit rate that the part is guaranteed to receive at, but I've seen comment online that it will work much faster. I would guess the limit is a requirement to get a minimum count in the bit counter (and the slow limit that at which it will overflow).

To me, the critical thing about this is that it works without needing any setup code from the 6502.

Neil

The circuit boards came back for both Neolithic Romless designs, along with a solder stencil for the STM-powered board. Hopefully I get some time to build at least one of them... I bought a new house yesterday so there may be some liftin' and carryin' to be done

Neil

Starting with all your 6502 paraphernalia, of course! And congratulations, BTW!

(Regarding the new PCB's, I mean! Oh, and the new house, too, I guess... )

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Good compliment to modern day core memory.

Even MRAM will want to be programmed at least once.
21 Address 8+8 Data is a few more 3.3V inputs than
can be twiddled by a lonesome Pi.