I'm in the layout and routing stage of my next SBC. This one is quite a bit larger than the others I've done in the past. It's a 2-layer board that also contains some headers (or slots). I got most of the board done with manual tracing (they removed the autorouter in KiCad 5...which may be a good thing for me).

Actually got about 2/3's done when I realized that in order to finish the last 1/3, I would need an obscene amount of via's. I was quite proud that I had almost no via's up to that point.

I also have an Apple IIe motherboard I am studying for reference. I noticed they used the "classic" pattern of horizontal traces on the top layer and vertical traces on the bottom.

Frustrated, I deleted all of my traces to start again. I also moved my components around to try for a better layout. What confuses me is that the A2 seemed to put all of the components upside down (pin 1 facing down). Also, none of the components run perpendicular to each other. They are all parallel (vertically oriented). Which I really like. Having OCD I'm really attracted to things that are symmetrical.

I'm going to take a multimeter and see if I can determine how they ran those traces. In the meantime, do you have any suggestions on how I can achieve something similar?

Board size is obviously an issue but I'm not interested in having a super tiny board. Even if it means costing a little more.

Could I skip the ground traces and just wait until the last minute after I do a ground pour? Then connect them to the pour? Or, should I always do both power traces first?

I did, however, use a much thicker trace for the power lines.

Oh, one more thing...I seemed to notice that the A2 board doesn't have traces BETWEEN pins. Not that I can see. This is even more amazing if you ask me because I was running traces between pins and I still couldn't finish. :-/

Thanks for any tips!

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Cat; the other white meat.

Showing your base schematic would likely help... mainly to see how many chips and their sizes. Clock speed can also play a factor in the layout. For a 2-layer board, the horizontal/vertical separation is common, but you can also mix them a bit... and also have some full traces between pins on the same side. You can look at Daryl's SBC2.5 for a nice clean reference.

The other option is to use a 4-layer board... which would give you a ground and power plane and really simplify the rest of the layout. My last PCB was a 4-layer... and having made 3 completed boards, I don't see myself going back to a 2-layer board for any similar future projects. VIAs are fine in my view... and mostly necessary as well for a good layout. My last project had 349 holes... mostly for components (all DIP) but quite a large number of VIAs as well... around 76 methinks.

Not sure this really helps you that much, but I've also changed physical layout to reduce board trace complexity.. and even changed the pins on a resistor network (SIP) to make the traces shorter and eliminate having to circle around things. The same can be said for logic chips, i.e., 4-gates in a single DIP, you can change which one goes where in the schematic to make the board layout easier/cleaner. There's a lot of things you can do on the schematic that can help reduce the layout complexity, including rotating parts, etc.

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Regards, KM
https://github.com/floobydust

One question: what are you trying to achieve? A beautiful design? Or are you actually struggling to route the board? I was concerned about vias in my boards, but apparently they are never really an issue at single digit Mhz speeds, and probably faster.

Horizontal traces on one side and vertical on the other is a great tool, even if that does mean you end up with many vias. This is especially true when using PLCC (socketed) parts. A 4 layer board is definitely something to think about.

When it comes to beauty I'm in awe of a really good board. Eg. the Amiga 4000 board, with it's 32bit busses and many, many QFPs/PLCCs and it fits on 4 layers. Leaves me with a massive respect for the guys who laid it out. If only my boards looked as good.

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8 bit fun and games: https://www.aslak.net/

It would be handy to see the schematic.

Some choices might be made with respect to chips too. For instance, GALs are great for glue as the pins can be re-defined to help with layout. As well, substituting 74X245s for 74x244s can help too (just tie the direction line to ground or Vcc as required) or 74x574s for 74x374s. Other chip choices could help too.

Also, remember that address lines and data line are arbitrary for RAM chips. It does not mater how you connect them as long as you don't mix data and address. Data goes to data and address goes to address, but order is arbitrary. It's not so with ROM chips though.

Vias are not much of an issue on 2-layer boards, but they actually are on 4-layer boards. On 4-layer boards they cause discontinuities in the return paths through the ground plane which introduces sudden impedance changes. If they are close together then can also create breaks/slots in the ground and voltage planes which will affect other signals not associated with the one requiring the via. There are a number of rules for using vias in 4+ layer designs and the number one rule is to minimize them. But for 2-layer they are generally fine.

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Bill

Thanks for all of the replies.

Unfortunately, I'm not at my normal computer so I don't have the schematic at hand. But, 90% of it is the 6502 computer on the primer.

http://wilsonminesco.com/6502primer/potpourri.html

I changed a few things about it (added four slots) but it's basically that computer.



A little of both, actually. Mostly struggling with the design. My design is going to run in the single digit MHz range. I thought about using 4 layer and probably will for my next board. My next board is going to use several PLCC's and surface mount.

I will study some more designs and see what the others look like.

Thanks!

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Cat; the other white meat.

BTW...WOW. I've seen that site before but forgot about it. That's amazing.

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Cat; the other white meat.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for the tips Garth!

Three traces between pads??? Wow. I think one other place I messed up is that in KiCad you can specify design rules and I was way too conservative. I will try to follow the limits set by my PCB house better (JLCPCB). Their specs are:

https://jlcpcb.com/capabilities/Capabilities

So it looks like they can do traces down to 3.5mils for 4+ layer and 5mills for 2 layer. However, I don't know if they have an extra charge when you get that close to the extreme.

Thanks.

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Cat; the other white meat.

If its of use to you, I have a library of 6502-related parts for KiCad here: https://github.com/Alarm-Siren/6502-kicad-library/
Amongst other things, it includes all packages of the modern WDC MPUs, MCUs and Peripheral chips.

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Want to design a PCB for your project? I strongly recommend KiCad. Its free, its multiplatform, and its easy to learn!
Also, I maintain KiCad libraries of Retro Computing and Arduino components you might find useful.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Here is a WIP screenshot.

I'm almost finished with the routing! Well, 3/4 done I suppose.

I will post schematics later. Now, I have to head to the movies with the family.

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Cat; the other white meat.

I would like to give some advice as the design looks clean and will probably work. But I'd be willing to bet, especially with only a 2 layer board and only 1 VCC/GND each to the expansion connectors, that as soon as you start actually plugging in expansion boards you will face failure due to noise issues from the voltage drop...

The advice has been given before, and I'll +1 it: do a 4 layer board. All of them. Your mainboard, and your expansion boards. If you do this, you may get away with only 1 VCC/GND per expansion board since it's slower speed and 5v CMOS.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Looking at what I can see, the supply and 0V/GND tracks need to be wider at the very least. Greater cross section means lower resistance and lower impedance. Aim for these to be at least 3mm wide. But where you have room, go even wider.

Have you ever heard of the star system? Although on a double layer board a true star power and ground system is not practical, some of the principles can be used. Separate high current feeds from more sensitive signal lines where you can. The common point should be at the regulator or bulk decoupling capacitor on the output of the regulator, or where there is no regulator, at the bulk decoupling capacitor connected across the input power terminals. Where possible, the supply and the ground tracks should take a similar route. Try to route both supply and ground so they go the shortest distance to each location. Think of it being a bit like a tree, with branches splitting off the trunk, etc...

On your expansion slots, what is the reason for including the higher order address lines if you have provided address decoded selection signals?

I would add at least two supply and two 0V/GND pins per expansion slot connector. More if you can.

Good luck

Mark

Thanks again, everyone, for the advice. This really helps me learn. I have attached the mostly finished schematics. I may "pretty it up" a little later but you get the idea.



I was wondering about that as well. I thought I would put some large caps near the power connector to help with the boards. Also, keep in mind, that this is just a hobby so I'm really curious as to how far I can push it. For example, the first expansion board I plan on making is a serial board (using the NXP). That's one reason I have two resets on board. RESET and /RESET.

FYI, I'm designing a "big board" computer as well. Hopefully, similar to the actual Apple IIe with 8 slots. So this starter SBC will, again hopefully, teach me what not to do.



Yeah, 1 MHz is my target speed. I will try and push it to see how far I can get.
I've really considered 4 layer. I wanted a few boards under my belt before I went to 4 layer. But that's only part of the reason. The other is cost. While prices have dropped, a 4 layer board is literally 3 times the cost. Well, maybe not 3 because I could shrink the design down a lot with the extra layers.

On the books is a surface mount design using the '816. I will certainly do 4 layer on that one.




I've taken this to heart and I'm making the traces much wider. As wide as I can without major changes to the (mostly) done layout.



Thanks again. I've heard of the star system, but haven't studied it in detail. Still learning all of this. I will look into it more.



Hmmm. Well, truth be told, I included them because that's what Apple did and I like the idea of "full access" to the CPU. I hate to keep bringing up the Apple II, but it really is the design I mostly aspire to learn. The "A" and "B" lines are literally because I had nothing else to put on there. LOL! I so thought..."Hey! Why not give the cards two lines to use for communicating with each other!". Hey, it was a great idea in my head. Although, after reading what you've said, I probably should have made them more power lines.



Certainly noted for my next design where I plan on using full blown 50 pin edge connectors. I really just want to finish this and move on. But you can bet on the next one, I will follow your advice.




Thanks for the encouragement!

My plan is to send this design to the PCB house this week. Depending on how tomorrow turns out. But either way, I expect to have this thing in my hands in a few weeks.

_________________
Cat; the other white meat.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?