Yeah that’s exactly what the oscilloscope showed under test. As long as the clock pulse executes immediately after the direction change, it seems fine. It’s a big, ugly hack. But, surprisingly reliable probably outside of crazy EMI conditions.

Changing up the algorithm would be nice. It’s current ...

I do have to ask, though, why your connection to the Arduino doesn't have either the R/W or the /OE and /WE lines connected? How does it know what type of cycle is intended?

Heh, the entire system with the Arduino is a pretty hacky. But, somehow does work. It uses the three address lines and #IO ...

one of their commercially sold reference SBCs was recently found to use a CD4000-series

Oof . That's pretty discouraging.

Thanks again for posting your timing examples. I think I get what you're going for. I took some time to play around with different setups and I've come up with a new layout ...

You have Phi1 (to the bank address latch) delayed one gate from Phi2, and the latch itself takes about another gate delay to actually close its inputs.

Huh... well shoot. That gating was actually something I tried to copy from WDC's SBC exactly as-is. I figured it would work without looking much ...

I'll repost here my 3, 4, and 5-chip glue logic examples for '816 systems.

Wow, thanks for posting that. I'll need to study it when I'm not so tired :mrgreen: .

Pretty much, I was following WDC's design straight out of the datasheet. Now that you mention it, the bus transceiver makes more sense ...

What's the total gate delay from A16...23 to the RAM and IO chip enables? It looks awfully long; but if you're really running only 2.28MHz, the processor's maximum t ADS of 30ns plus the VIA's t ACR of 10ns should leave you with 180ns for that long chain of glue logic

Yeah, that is something I ...

Make sure there is no way to write to RAM when phase 2 is low. Looking at the timing diagrams in the data sheet, you will see that the address lines are not guaranteed to be valid and stable before the R/W goes low; so it is possible to write to unintended addresses. This information is in the 6502 ...

Hi everyone. Long time lurker, first time poster here.

I've been trying to design a 65C816 computer for a while now and I'm running into some issues that I think go beyond a mistaken connection. I've sent two versions of this computer in for fabrication. The first board didn't work at all. The ...