65C816 board glue logic issues?

[Chromatix]

You should be able to improve that situation as follows:

Code: Select all

1: Raise clock, beginning Phi2 phase.
2: Check address.
3: If address matches for a read, perform internal action and place data on pins.
4: If address matches, set data pins to output mode.  (This ordering avoids a double transition on the bus.)
5: Lower clock, ending Phi2 phase.  This instructs the CPU to latch the data on the bus.
6: Set data pins to input mode immediately after lowering clock, the sooner the better.

The only reason your current scheme works is because the bus has some parasitic capacitance which tends to keep voltages where they are unless actively driven elsewhere.

[HalfBurntToast]

Yeah that’s exactly what the oscilloscope showed under test. As long as the clock pulse executes immediately after the direction change, it seems fine. It’s a big, ugly hack. But, surprisingly reliable probably outside of crazy EMI conditions.

Changing up the algorithm would be nice. It’s current state was a long process of compiling to assembly and going instruction-by-instruction to optimize the speed as much as possible. The shortest execution loop is 7 instructions, which gives me the 2.28MHz with the Arduino’s crystal.

But, for the time being, I’m just trying to get the glue logic right . I’m already down about $60 on failed boards + components. This next build is going to be fully through-hole, so at least I can socket and reuse the components if there’s another problem.