Since your backplane is a bus with multiple stubs (the sockets and the cards plugged into them), ideally it would be terminated at both ends to match the characteristic impedance of the bus, which is an unknown. All high-speed buses I've seen place the termination at the bus ends, not the stubs ...

I’d think very carefully about what you are trying to accomplish before committing to this route.
This is why I'm taking my time to research the subject. Thank you for your answers, it highlights a lot of things I need to take into consideration.

About termination, if there are none at the ...

See the 6502 primer's page about construction for good AC performance, at http://wilsonminesco.com/6502primer/construction.html . It has good links to lectures and articles about termination; but I also just expanded it to cover the matter of connector pinout, since you only have power and ground ...

I know it's an old thread, but it's relevant to my current project. I'm in the process of designing a backplane using 62-pin ISA card edge connectors. It gives me plenty of pins to have a 65816 CPU board with all associated signals. I have 8 slots, 22mm on-center, and the total trace length from end ...

I admit I don't full understand what has been posted since my last post, but I do get the general gist of it.

Understandably, timing is everything. I think I was looking for a simple solution to a rather complex problem. I definitely will need to do more homework on this.

I want to thank all ...

Hi BDD,
This circuit has been put into practical application in POC V1.3 .
I implemented your circuit to try it out. Except for a minor change, as you can see in the attached diagram. I replaced the 74AC109 with a 74AC112 (because that's what I had on hand), which is functionally the same, except ...

Hi Jeff,
The hardware page on his website includes a section explaining Clock Generation, and the clock-stretch circuit gets no attribution -- a trifling oversight perhaps. I'm certainly not the only person capable of coming up with this particular approach. And I am indirectly acknowledged in this ...

Hi Adrien,
The way to determine the maximum frequency for a component is to look at all the signals going into this chip and their timings. Let's run through a quick example. Starting from the CPU, western design center gives you timings for the address bus / read-write, which are 10 to 30ns. That ...

I've designed a few PCB variations of my 65C02 SBC. All run at 2MHz safe speed. The reason why I thought I needed the slower speed was for slower I/O, like the AY-3-8910 PSG and TMS9918A VDP.

I've read a bit on the subject of wait states and clock stretching. I can't say I understand fully and ...

There is nothing worse than spending a large chunk of time scanning multiple sheets/pages or a large diagram looking to find a signal tag and not being able to find it. Or worse, with a signal used in multiple places, looking for one that you expect, but can’t find, because it does not exist ...

With KiCad, you can co up to E size (34" x 44"), and even customize your size. I'm sure most programs can do this though. But I'll have to try to see if KiCad can segment into 8.5" x 11x sheets.

Would a single large schematic be preferable when posting?

Thank you for the example. I shall use it as inspiration when I redraw mine.

Not at all, I just learned something quite valuable in schematic design today. I will do better next time.

... take the time to check the details if you draw an actual schematic, instead of just a netlist written around boxes. When the connections just have tags, we have to look everywhere for the matching tag. Valid point. I'll be careful in my designs next time.
... but one easy thing I see that can ...